超低比导通电阻槽型功率MOS新结构与机理研究

发布时间：2018-10-17 18:00

【摘要】：功率MOS器件作为电力电子系统的核心,其研究热点之一为实现低功耗。其中,功率MOS的总功耗主要包括静态功耗和动态功耗,器件的静态功耗主要是通过导通电阻来衡量,动态功耗通过器件的栅漏电容来衡量。为了降低功率MOS的导通电阻和栅漏电容,本文提出了两种新型功率MOS器件,并对其静态特性(包括正向导通特性和耐压特性)、动态特性及可行的工艺实现方案进行了研究。仿真结果表明,两种新结构极大地改善了器件的性能,在保证器件耐压的同时显著地降低了器件的功耗。1.提出一种具有分离栅的超低比导通电阻和超低动态损耗功率FINFET器件。该结构的特征为具有鳍型栅和分离栅,鳍型栅从三个维度包围P-well区域,与源电位电气连接的分离栅设置在漂移区的两侧并且与漂移区用楔形的氧化层隔离开。第一,鳍型栅结构增大了沟道的宽度、调制了电流的分布,因而降低了器件的比导通电阻、提高了器件的跨导。第二,分离栅结构减小了器件栅漏交叠,因此栅漏电容和开关损耗也极大地降低。第三,分离栅结构作为源场板辅助漂移区的耗尽,从而提高了器件的漂移区掺杂浓度,进而进一步降低器件的比导通电阻。第四,分离栅结构作为源场板,调制了源端和漏端的高电场,使漂移区的电场分布更均匀,从而保证了器件的耐压。仿真结果显示,在保持80V级别的耐压下,提出的新结构与常规结构和常规超结器件相比,导通电阻分别下降了60%和47%。同时,新结构的栅漏电荷与没有分离栅的结构相比下降了55%。2.提出了一种具有电荷积累层的超低比导通电阻VDMOS器件。结构特征为具有一直延伸到漏端的延伸栅结构,且延伸栅中包含两个PN结。一方面,在正向导通状态,在延伸栅的两侧壁形成电子积累层,从而引入两条从源端到漏端的低阻电流通路。这种形成的电流通路不仅极大地降低器件的导通电阻,而且还使得器件的导通电阻对漂移区掺杂浓度的依赖减弱。另一方面,在耐压状态下,延伸栅内部的N条会耗尽漂移区的N条,从而使得器件的漂移区掺杂浓度提高,进一步降低器件的导通电阻。特别需要说明,延伸栅内部的两个PN结具有十分重要的作用。在正向导通状态,其中一个PN结反偏承受器件的栅漏之间的电压,减小了栅的泄漏电流;在耐压状态下,另一个PN结承受漏与栅之间的高电压,保证了器件具有高的击穿电压。由于器件延伸栅一直延伸到器件的漏端,所以新结构具有较大的栅漏电容,导致开关特性的退化,所以新结构适合运用于中频和低频应用范围。仿真结果表明,新结构与常规超结器件相比,在保持800V级别的耐压时,比导通电阻下降了80%。
[Abstract]:As the core of power electronic system, power MOS device is one of the research hotspots to realize low power consumption. Among them, the total power consumption of power MOS mainly includes static power consumption and dynamic power consumption, the static power consumption of the device is mainly measured by on-resistance, and the dynamic power consumption is measured by the gate leakage capacitance of the device. In order to reduce the on-resistance and gate leakage capacitance of power MOS, two new types of power MOS devices are proposed in this paper. The static characteristics (including forward on-on characteristics and voltage-resistant characteristics), dynamic characteristics and feasible process implementation schemes are studied. The simulation results show that the two new structures can greatly improve the performance of the device and reduce the power consumption of the device significantly while maintaining the voltage resistance of the device. An ultra-low specific on-resistance and ultra-low dynamic loss power FINFET device with separation gate is proposed. The structure is characterized by having a fin gate and a separation gate. The fin gate surrounds the P-well region from three dimensions. The separation gate electrically connected with the source potential is arranged on both sides of the drift region and separated from the drift region by a wedge oxide layer. First, the fin gate structure increases the channel width and modulates the current distribution, thus reducing the specific on-resistance of the device and increasing the transconductance of the device. Secondly, the gate leakage and the switching loss are greatly reduced by the separation gate structure. Thirdly, the separation gate structure is used as the depletion of the source field-assisted drift region, thus increasing the doping concentration in the drift region of the device, and further reducing the specific on-resistance of the device. Fourth, the separation gate structure acts as the source field plate, modulates the high electric field at the source and drain ends, and makes the electric field distribution in the drift region more uniform, thus ensuring the voltage resistance of the device. The simulation results show that the on-resistance of the new structure is reduced by 60% and 47%, respectively, compared with the conventional structure and the conventional overjunction device. At the same time, the gate leakage charge of the new structure is 55. 2% lower than that of the structure without separate gate. An ultra-low specific on-resistance VDMOS device with charge accumulation layer is proposed. The structure is characterized by an extended gate structure with an extended gate extending to the leakage end and two PN junctions in the extended gate. On the one hand, an electron accumulation layer is formed on both sides of the extended gate in the positive guide state, thus introducing two low-resistance current paths from the source to the drain. The resulting current path not only greatly reduces the on-resistance of the device, but also weakens the dependence of the on-resistance of the device on the doping concentration in the drift region. On the other hand, in the voltage-resistant state, the N strip inside the extended gate will exhaust the N strip in the drift region, thus increasing the doping concentration in the drift region of the device and further reducing the on-resistance of the device. In particular, the two PN junctions within the extended gate play a very important role. In the positive-guide state, one of the PN junctions inversely deflects the voltage between the gate leaks, thus reducing the gate leakage current, while in the voltage-tolerant state, the other PN junction withstands a high voltage between the drain and the gate, which ensures the device has a high breakdown voltage. Because the extended gate of the device extends to the leakage end of the device, the new structure has a large gate leakage capacitance, which leads to the degradation of the switching characteristics, so the new structure is suitable for use in if and low frequency applications. The simulation results show that compared with the conventional overjunction devices, the new structure decreases the on-resistance by 80% when the voltage is maintained at 800V level.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386.1

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