FPGA功耗早期评估模型研究与实现
发布时间：2018-10-17 20:44
【摘要】：现场可编程门阵列(FPGA)由于其设计成本低、可重复编程等优点被广泛应用。随着工艺进入纳米尺寸,FPGA集成度越来越高,导致设计的功耗问题更加突出。商用FPGA功耗评估工具包括Xpower和EPE,其中Xpower在布局布线后进行功耗评估,结果精确；EPE在设计早期评估功耗,精度不高。其他的功耗评估研究工作在设计不同层次进行,也存在精度不高的问题。本文对FPGA功耗早期评估进行了建模与实现。在介绍了FPGA架构和功耗来源的基础上,考虑到商用FPGA电路结构的复杂性,本文在电路综合完成后对FPGA功耗进行评估,将FPGA功耗分为可编程逻辑资源和时钟／互连资源功耗,并分别对两部分功耗进行建模。对于可编程逻辑资源,建立了基于开关活动性和资源使用数的动态宏单元功耗模型。其中设计了基于ARMA信号的随机激励产生器,并使用基于概率传递的方法评估电路开关活动性,通过编写perl脚本解析网表获取资源使用数。对于时钟／互连部分,在分析单条互连功耗随模块间距离线性增加的基础上,建立了基于面积估算的开关级功耗模型。其中为了抽取不同类型互连的等效电容,本文采用一种基于差值和非线性拟合的方法。此外,为了验证功耗模型的正确性,本文搭建了仿真验证平台,对Virtex-6 XC6VLX760芯片进行功耗评估。该平台读入综合后的网表文件和激励信号,计算电路节点开关活动性和资源使用数。对MCNC的20个基准电路分别采用本文模型与Xpower软件的结果进行对比,表明上述模型的最小误差为3.62%,最大误差为45.3%,平均误差为22.8%。与同类文献对比实验结果显示,在抽象层次相同的情况下本文模型精度比同类文献高15%,表明本文功耗模型能够精确的评估功耗。
[Abstract]:Field Programmable Gate Array (FPGA) is widely used because of its low design cost and repeatable programming. As the process enters into nanometer size, the integration of FPGA becomes more and more high, which leads to the problem of design power consumption becoming more and more prominent. Commercial FPGA power evaluation tools include Xpower and EPE, where Xpower is used to evaluate power consumption after layout and wiring, and EPE is used to evaluate power consumption in the early stage of design. Other research work on power evaluation is carried out at different levels of design, which also has the problem of low precision. In this paper, the early evaluation of FPGA power consumption is modeled and implemented. Based on the introduction of FPGA architecture and power source, considering the complexity of the circuit structure of commercial FPGA, this paper evaluates the power consumption of FPGA after circuit synthesis, and divides the power consumption of FPGA into programmable logic resources and clock / interconnect resources power consumption. The two parts of power consumption are modeled separately. For programmable logic resources, a dynamic macro cell power model based on switch activity and resource usage is established. A random excitation generator based on ARMA signal is designed, and the probability transfer based method is used to evaluate the switch activity of the circuit. The perl script is written to analyze the network table to obtain the resource usage. For the clock / interconnect part, a switching level power model based on area estimation is established on the basis of analyzing that the power consumption of single interconnect increases linearly with the distance between modules. In order to extract the equivalent capacitance of different types of interconnection, a method based on difference and nonlinear fitting is used in this paper. In addition, in order to verify the correctness of the power model, a simulation verification platform is built to evaluate the power consumption of Virtex-6 XC6VLX760 chip. The platform reads the network table file and the excitation signal, calculates the switch activity and the resource usage of the circuit node. The results of 20 reference circuits of MCNC are compared with the results of Xpower software. The results show that the minimum error of the above model is 3.622, the maximum error is 45.3 and the average error is 22.8. The experimental results show that the accuracy of the proposed model is 15% higher than that of the similar literatures under the same abstraction level, which indicates that the proposed model can accurately evaluate the power consumption.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN791
本文编号：2277916
[Abstract]:Field Programmable Gate Array (FPGA) is widely used because of its low design cost and repeatable programming. As the process enters into nanometer size, the integration of FPGA becomes more and more high, which leads to the problem of design power consumption becoming more and more prominent. Commercial FPGA power evaluation tools include Xpower and EPE, where Xpower is used to evaluate power consumption after layout and wiring, and EPE is used to evaluate power consumption in the early stage of design. Other research work on power evaluation is carried out at different levels of design, which also has the problem of low precision. In this paper, the early evaluation of FPGA power consumption is modeled and implemented. Based on the introduction of FPGA architecture and power source, considering the complexity of the circuit structure of commercial FPGA, this paper evaluates the power consumption of FPGA after circuit synthesis, and divides the power consumption of FPGA into programmable logic resources and clock / interconnect resources power consumption. The two parts of power consumption are modeled separately. For programmable logic resources, a dynamic macro cell power model based on switch activity and resource usage is established. A random excitation generator based on ARMA signal is designed, and the probability transfer based method is used to evaluate the switch activity of the circuit. The perl script is written to analyze the network table to obtain the resource usage. For the clock / interconnect part, a switching level power model based on area estimation is established on the basis of analyzing that the power consumption of single interconnect increases linearly with the distance between modules. In order to extract the equivalent capacitance of different types of interconnection, a method based on difference and nonlinear fitting is used in this paper. In addition, in order to verify the correctness of the power model, a simulation verification platform is built to evaluate the power consumption of Virtex-6 XC6VLX760 chip. The platform reads the network table file and the excitation signal, calculates the switch activity and the resource usage of the circuit node. The results of 20 reference circuits of MCNC are compared with the results of Xpower software. The results show that the minimum error of the above model is 3.622, the maximum error is 45.3 and the average error is 22.8. The experimental results show that the accuracy of the proposed model is 15% higher than that of the similar literatures under the same abstraction level, which indicates that the proposed model can accurately evaluate the power consumption.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN791
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