快速瞬态响应无片外电容LDO研究与设计

发布时间：2018-10-18 12:42

【摘要】：伴随着智能终端设备,如手机、手环、手表、电视以及日趋火爆的智能家居等迅速发展,各类电子产品已经融入人们不可或缺的日常生活中。电源管理芯片作为电子产品的核心成分,不但使得产品体积减小、成本降低,功耗也在不停的降低,迎合了如今低碳环保的国际形势。本文设计了一款无片外电容LDO,主要提升其瞬态特性与稳定性,给出了详细的设计流程,分别对误差放大器、调整管、瞬态加强电路进行优化与设计。这些优化设计有效提高了无片外电容的稳定性,降低了芯片失效与逻辑混乱的风险。研究了可以提高瞬态响应的方法。通过分析几类误差放大器结构特点,选择合适结构对参数进行优化与设计,通过提高增益与摆率来加强瞬态响应。论文研究了功率管类型,并提出本文设计方案,通过理论推导,对功率管参数进行优化。论文研究了无片外电容LDO的瞬态特性。本文首先分析传统LDO片外大电容作用,为无片外电容LDO研究做理论基础,重点研究了无片外电容LDO瞬态特性。针对影响瞬态特性的重要因素,提出一种无片外电容LDO瞬态加强电路结构。该方法在负载变化时,会检测到负载变化情况以电压形式输出,再通过RC微分电路将检测电压信号变成尖峰脉冲,通过瞬间导通MOS管转换为电流信号,最后叠加到误差放大器的尾电流上,通过加强误差放大器的摆率来提高功率管充放电速度,减小过冲电压。论文研究了LDO的稳定性。通过对本文的结构进行小信号分析,推导零点与极点公式,在系统的第一个主极点后面采用RC电路进行左半平面零点补偿,增加相位裕度提高稳定性。最后,本文基于0.5μmBICMOS工艺进行设计,通过Hspice平台仿真验证,结果表明,负载电流经过1μs从1mA～100mA变化,下冲145mV,经过1μs从100mA-1mA变化,过冲为129mV。在静态工作时,静态功耗为50μA,负载响应时间最大仅为1.3μs,输入信号3dB带宽为1668Hz,0dB带宽高达30megHz,且整个补偿电容仅为4pF。
[Abstract]:With the rapid development of smart terminal devices, such as mobile phone, bracelet, watch, TV and the increasingly popular smart home, all kinds of electronic products have been integrated into people's indispensable daily life. As the core component of electronic products, power management chip not only reduces the volume, cost and power consumption of products, but also meets the international situation of low carbon environmental protection. In this paper, an off-chip capacitive LDO, is designed to improve its transient characteristics and stability, and the detailed design flow is given. The error amplifier, adjusting tube and transient strengthening circuit are optimized and designed respectively. These optimized designs can effectively improve the stability of off-chip capacitance and reduce the risk of chip failure and logic chaos. The method of improving transient response is studied. By analyzing the structural characteristics of several kinds of error amplifiers, the parameters are optimized and designed by selecting a suitable structure, and the transient response is enhanced by increasing the gain and the pendulum rate. In this paper, the type of power transistor is studied, and the design scheme of this paper is put forward, and the parameters of power tube are optimized by theoretical derivation. In this paper, the transient characteristics of a non-chip capacitive LDO are studied. In this paper, we first analyze the effect of traditional LDO off-chip large capacitance, which provides a theoretical basis for the study of out-of-chip capacitance (LDO), focusing on the transient characteristics of LDO. In view of the important factors affecting the transient characteristics, a transient strengthening circuit structure without off-chip capacitance LDO is proposed. In this method, when the load changes, the load changes will be detected in the form of voltage output, and then the detection voltage signal will be turned into a peak pulse through RC differential circuit, and the MOS tube will be converted into a current signal through the instantaneous conduction of the MOS tube. Finally, it is superimposed on the tail current of the error amplifier to increase the charge and discharge speed of the power tube and reduce the overshoot voltage by strengthening the swing rate of the error amplifier. The stability of LDO is studied in this paper. Through the small signal analysis of the structure in this paper, the formula of zero and pole is deduced, and the RC circuit is used to compensate the left half plane zero after the first main pole of the system, which increases the phase margin and improves the stability. Finally, the design is based on 0.5 渭 mBICMOS process. The simulation results on Hspice platform show that the load current changes from 1mA~100mA to 145mV by 1 渭 s, and from 100mA-1mA to 129mV by 1 渭 s. In static operation, the power consumption is 50 渭 A, the maximum load response time is 1.3 渭 s, the input signal 3dB bandwidth is 1668 Hz, the bandwidth is 30 megHz, and the compensation capacitance is only 4 PF.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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