高速高精度流水线ADC中运算放大器的设计

发布时间：2018-10-20 11:16

【摘要】：自从美国德州仪器公司的杰克2基尔比在1958年向人们展示了第一块集成电路以来,集成电路作为一份全新的产业诞生了。在过去的50多年中,电子产品,特别是以集成电路芯片为核心的电子产品层出不穷。随着时代的进步,人们对电子产品的性能要求越来越高,这也就对集成电路芯片的性能提出了更高的要求。作为构成模拟系统和数模混合系统的重要基本单元,算放大器如何设计和优化运,是整个芯片系统设计中的重要内容。ADC(模拟-数字转换器),作为连接模拟信号和数字信号的桥梁,在数字电路和数字信号处理技术高速发展的今天,重要性越来越突出。流水线ADC(Pipelined ADC)是高速高精度ADC设计中普遍选用的结构,因为它能很好的兼顾速度、功耗、面积等方面的要求。在流水线ADC电路结构中,核心模块之一就是运算放大器,它的性能对流水线ADC的最终性能有直接的影响。因此,研究和设计高增益、宽带宽的运算放大器对实现高速精度流水线ADC意义重大。本文首先设计了一款应用于流水线ADC中的全差分两级运算放大器,第一级电路采用了折叠式共源共栅结构,第二级电路则选用了简单共源放大结构。为了稳定输出共模电压,在两级中都加入了共模负反馈电路,其中第一级使用了结构简单但很有效的交叉耦合负反馈。在仿真验证了设计的正确性之后,进行了版图的设计。仿真结果显示所设计的运算放大器直流增益为92.8 d B,单位增益带宽为195.5 MHz。该设计采用TSMC0.18μm 1P6M工艺流片实现,并设计了用于测试的电路板对实际的芯片进行了测试,测试结果显示运算放大器直流增益为83 d B,单位增益带宽为170 MHz。针对一款14bit 100MS/s流水线ADC的设计要求,本文采用增益自举(Gain-boosting)结构设计了一款单级共源共栅运算放大器,在不改变原运算放大器的直流工作状态的情况下,增益自举技术能大大提高运算放大器的增益。在仿真验证了设计的正确性之后,进行了版图的设计。仿真结果显示所设计的运算放大器直流增益为100.6 d B,单位增益带宽为968.9 MHz。
[Abstract]:Since Jack 2 Kilby of Texas Instruments showed the first integrated circuit in 1958, integrated circuit has been born as a new industry. In the past 50 years, electronic products, especially IC chips as the core of electronic products emerge in endlessly. With the progress of the times, the performance requirements of electronic products are becoming higher and higher, which puts forward higher requirements for the performance of integrated circuit chips. As an important basic unit of analog system and digital-analog hybrid system, how to design and optimize the amplifier is calculated. As a bridge between analog signal and digital signal,. ADC (is an important content in the whole chip system design. With the rapid development of digital circuit and digital signal processing technology, the importance is more and more prominent. Pipelined ADC (Pipelined ADC) is a widely used structure in high speed and high precision ADC design, because it can take into account the requirements of speed, power consumption, area and so on. In the pipelined ADC circuit structure, one of the core modules is the operational amplifier. Its performance has a direct impact on the final performance of the pipeline ADC. Therefore, it is of great significance to study and design high gain and wide bandwidth operational amplifiers to achieve high speed precision pipeline ADC. In this paper, a fully differential two-stage operational amplifier used in pipelined ADC is designed. The first stage of the circuit adopts a folded common-source common-gate structure, and the second stage of the circuit uses a simple common-source amplifier. In order to stabilize the output common-mode voltage, a common-mode negative feedback circuit is added in both stages. In the first stage, a simple but effective cross-coupled negative feedback is used. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 92.8 dB and the unit gain bandwidth is 195.5 MHz.. The design is implemented by TSMC0.18 渭 m 1P6M technology, and the circuit board used for testing is designed to test the actual chip. The test results show that the DC gain of the operational amplifier is 83 dB and the unit gain bandwidth is 170 MHz.. According to the design requirements of a 14bit 100MS/s pipelined ADC, a single-stage common-grid operational amplifier is designed using gain bootstrap (Gain-boosting) structure, without changing the DC operating state of the original operational amplifier. The gain bootstrap technique can greatly improve the gain of operational amplifier. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 100.6 dB and the bandwidth per unit gain is 968.9 MHz..
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN722.77;TN792

【共引文献】