高性能ALU部件的时序和功耗优化

发布时间：2018-10-22 09:49

【摘要】：性能和功耗是评价一款芯片优良的重要指标。随着芯片的集成度越来越高,工艺的特征尺寸越来越小,使得芯片设计的复杂程度成倍增长,导致芯片物理设计的工作压力越来越大。同时,电压降、串扰、绕线、拥塞等因素对于芯片性能和功耗的影响越来越大,这些因素对芯片性能和功耗优化工作提出了新的挑战。本文对FT-DX芯片ALU部件的固化设计做了细致的研究,为了缩短设计周期,并且取得较好的时序结果,对ALU部件的物理设计采用了半定制设计方法,使用脚本结合EDA工具完成初步优化,对其中的关键路径和局部时钟树重构做了手工的优化。通过本文方法的优化,ALU部件的时序结果与单纯使用EDA工具进行优化的结果相比,时序优化了31%,消除了97%的建立时间检查违反路径,迭代周期缩减了约50%。本文对扫描链在物理设计中的影响进行了深入分析。为了减小扫描链路占用的布局资源,减小测试模式下扫描链路的时序违反和功耗,本文提出了一种结合扫描单元物理位置信息的扫描链定序方法。此方法通过减少扫描链路中插入的缓冲器数目和减少绕线,合理排列扫描单元连接顺序,来达到降低扫描链路占用的布线资源,减少测试模式下扫描链路保持时间检查违反和降低测试模式下扫描链路功耗的目的,并对传统的物理设计流程进行了改进。结合FT-DX芯片的ALU部件,对本文方法进行了实践检验,结果证明,本文的扫描链定序方法与传统方法相比,测试功耗降低了1.12%,总时序优化了4.1%。本文提出了一种通过缩减非关键路径上单元尺寸来降低功耗、减小保持时间检查违反和布局资源的方法。通过结合Power Explorer工具,缩减非关键路径上有优化余量的单元的尺寸的方法,对传统的物理设计优化流程进行了改进。结合FT-DX芯片的ALU部件对本文提出的尺寸缩减方法进行了实践检验,结果证明本文提出的方法确实可以有效降低非关键路径的功耗,比单纯使用Power Explorer工具进行功耗优化所取得的好处增加了一倍。
[Abstract]:Performance and power consumption are important indexes to evaluate a chip. With the increasing integration of the chip, the characteristic size of the process becomes smaller and smaller, which makes the complexity of the chip design increase exponentially, resulting in the working pressure of the chip physical design is increasing. At the same time, voltage drop, crosstalk, wire winding, congestion and other factors have more and more influence on chip performance and power consumption. These factors pose a new challenge to chip performance and power optimization. In this paper, the solidification design of ALU parts of FT-DX chip is studied in detail. In order to shorten the design period and obtain better timing results, the semi-custom design method is used for the physical design of ALU parts. The script combined with EDA tool is used to optimize the critical path and local clock tree by hand. Through the optimization of the method in this paper, the timing results of ALU parts are optimized by 31%, 97% of the setup time is eliminated, and the iteration period is reduced by about 50% compared with the results of simple optimization using EDA tools. In this paper, the influence of scanning chain on physical design is analyzed. In order to reduce the layout resource occupied by the scanning link and to reduce the timing violation and power consumption of the scan link in test mode, a scanning chain ordering method combining the physical location information of the scanning unit is proposed in this paper. By reducing the number of buffers inserted in the scanning link, reducing the winding and arranging the connection order of the scanning unit reasonably, the method can reduce the wiring resources occupied by the scanning link. The purpose of reducing scan link holding time in test mode to check violation and to reduce the power consumption of scan link in test mode is discussed, and the traditional physical design flow is improved. Combined with the ALU part of FT-DX chip, the method is tested. The results show that compared with the traditional method, the test power consumption is reduced by 1.12 and the total timing is optimized by 4.1. In this paper, we propose a method to reduce power consumption and hold time to check violations and layout resources by reducing cell size on non-critical paths. The traditional physical design optimization process is improved by using the Power Explorer tool to reduce the size of the unit with an optimization margin on the non-critical path. The size reduction method proposed in this paper is tested with the ALU part of FT-DX chip. The results show that the proposed method can effectively reduce the power consumption of non-critical path. The benefits of power optimization are more than double that of using Power Explorer tools alone.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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