低功耗高速时钟数据恢复电路
发布时间：2018-10-23 08:34
【摘要】：为了降低高速串行接口的时钟数据恢复(CDR)电路的功耗,在研究、分析现有时钟数据恢复结构的基础上,提出了一种新的时钟数据鉴相算法及其电路实现方法。新的电路设计仅使用一个高速采样时钟,比传统的鉴相电路减少一半的采样率,从而减少了前端采样模块的功耗。该鉴相算法采用统计方法减小鉴相时钟的噪声,进而达到很低的误码率。该鉴相算法可使用数字综合的方法实现,工作在较低的频率下,这样便于迁移到不同的工艺中。整个电路使用40nm工艺实现,实际芯片测试数据表明,使用该电路的接收端可以稳定工作在13Gb/s的速率下,功耗达到0.83p J/bit,误码率低于10E-12。
[Abstract]:In order to reduce the power consumption of the clock data recovery (CDR) circuit with high speed serial interface, a new clock data phase detection algorithm and its implementation method are proposed based on the analysis of the existing clock data recovery structure. The new circuit design uses only one high-speed sampling clock, which reduces the sampling rate by half compared with the traditional phase detection circuit, thus reducing the power consumption of the front-end sampling module. The phase detection algorithm uses statistical method to reduce the noise of phase detection clock and achieve a very low bit error rate (BER). The phase detection algorithm can be realized by digital synthesis, working at low frequency, which is easy to migrate to different processes. The whole circuit is implemented in 40nm technology. The actual chip test data show that the receiver using this circuit can work stably at the rate of 13Gb/s, and the power consumption is 0.83p / J / bit. the bit error rate is lower than 10E-12.
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院计算技术研究所;中国科学院大学;
【基金】：国家“核高基”科技重大专项课题(2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002,2012ZX01029-001-002-002,2014ZX01020201,2014ZX01030101) 国家自然科学基金(61521092,61133004,61173001,61232009,61222204,61432016) 863计划(2013AA014301)资助项目
【分类号】：TN402
[Abstract]:In order to reduce the power consumption of the clock data recovery (CDR) circuit with high speed serial interface, a new clock data phase detection algorithm and its implementation method are proposed based on the analysis of the existing clock data recovery structure. The new circuit design uses only one high-speed sampling clock, which reduces the sampling rate by half compared with the traditional phase detection circuit, thus reducing the power consumption of the front-end sampling module. The phase detection algorithm uses statistical method to reduce the noise of phase detection clock and achieve a very low bit error rate (BER). The phase detection algorithm can be realized by digital synthesis, working at low frequency, which is easy to migrate to different processes. The whole circuit is implemented in 40nm technology. The actual chip test data show that the receiver using this circuit can work stably at the rate of 13Gb/s, and the power consumption is 0.83p / J / bit. the bit error rate is lower than 10E-12.
【作者单位】： 计算机体系结构国家重点实验室(中国科学院计算技术研究所);中国科学院计算技术研究所;中国科学院大学;
【基金】：国家“核高基”科技重大专项课题(2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002,2012ZX01029-001-002-002,2014ZX01020201,2014ZX01030101) 国家自然科学基金(61521092,61133004,61173001,61232009,61222204,61432016) 863计划(2013AA014301)资助项目
【分类号】：TN402
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