硅基射频开关集成电路设计

发布时间：2018-10-25 20:03

【摘要】：随着无线通信市场的迅速发展,低成本与高集成度的射频收发机需求在不断增加。为了迎合这种趋势,互补金属氧化物半导体(CMOS)由于其优越特性而备受关注。然而,在实现全集成收发机这个目标上,CMOS工艺因其自身缺陷遇到了瓶颈,难以集成大功率器件,如开关与功率放大器。基于此,本文采用硅基SOI工艺设计一款大功率单刀五掷开关,对促进全集成收发机的实现具有重要意义。本文首先介绍了CMOS工艺下的射频开关技术,分析当前CMOS三阱工艺在设计开关电路时的物理局限性,并且加入硅基SOI工艺做为对比,阐述SOI工艺在射频开关设计上的优势地位。紧接着,通过分析串并式硅基开关的功率承载能力瓶颈,采用负压偏压方式控制开关晶体管关闭来提高开关的线性度。负压模块集成于SOI开关芯片中,由振荡器、时钟缓冲器以及负压电荷泵三者共同组成。其中的振荡器部分本文使用的是多谐振荡器电路,替换了经典负压模块中的环形振荡器,相比于后者,前者在低频及低工艺节点应用时具备更小的尺寸以及更好的稳定性。然后,根据SOI工艺库提供的开关晶体管建立了“导通”与“关闭”两种状态的等效集总模型,并给出各寄生参数的提取公式,通过与PDK晶体管的S参数仿真对比,验证了等效模型的准确性以及参数提取的正确性。等效模型的建立对开关晶体管尺寸的选取具有指导意义。最后,基于等效模型分析设计开关电路,并流片测试。制造的SOI开关芯片面积为1.6×0.6 mm2。在频率0.7~2 GHz范围内,测试插入损耗小于1.1 dB,测试隔离度大于27.5 dB,测试端口回波损耗大于17 dB,仿真的输入1 dB压缩点大于33 dBm(受矢网输出功率限制,实测大于16 dBm)。开关测试与仿真性能接近设计指标,验证了硅基材料实现大功率器件的可行性。
[Abstract]:With the rapid development of wireless communication market, the demand of low cost and high integration RF transceiver is increasing. In order to meet this trend, complementary metal oxide semiconductor (CMOS) has attracted much attention because of its superior characteristics. However, in order to achieve the goal of fully integrated transceiver, the CMOS process is difficult to integrate high-power devices, such as switches and power amplifiers, because of its own defects. Based on this, this paper designs a high-power single-pole five-throw switch using silicon-based SOI process, which is of great significance to promote the realization of a fully integrated transceiver. This paper first introduces the RF switching technology in CMOS process, analyzes the physical limitations of the current CMOS triple well process in the design of switching circuits, and adds the silicon-based SOI process as a comparison, and expounds the advantage of the SOI process in the design of RF switches. Then, by analyzing the bottleneck of power carrying capacity of series-parallel silicon based switch, the switching transistor shutdown is controlled by negative voltage bias to improve the linearity of the switch. The negative voltage module is integrated into SOI switch chip and consists of oscillator clock buffer and negative charge pump. In the part of the oscillator, the circuit of multivibrator is used, which replaces the ring oscillator in the classical negative voltage module. Compared with the latter, the former has smaller size and better stability in low-frequency and low-process node applications. Then, according to the switching transistor provided by SOI process library, the equivalent lumped model of "on" and "off" states is established, and the extraction formulas of each parasitic parameter are given. The simulation results are compared with those of PDK transistor. The accuracy of the equivalent model and the correctness of parameter extraction are verified. The establishment of equivalent model is of great significance to the selection of the size of switch transistors. Finally, the switch circuit is designed based on the equivalent model, and the parallel chip test is carried out. The area of SOI switch chip is 1.6 脳 0.6 mm2.. In the frequency range of 0.7 ~ 2 GHz, the test insertion loss is less than 1. 1 dB, the test isolation is greater than 27. 5 dB, the echo loss of the test port is greater than 17 dB, the input 1 dB compression point is greater than 33 dBm (limited by the output power of the vector network), Measured more than 16 dBm). The performance of switch test and simulation is close to the design index, which verifies the feasibility of silicon based material to realize high power device.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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