600V高雪崩耐量平面栅VDMOS器件优化设计
发布时间：2018-10-25 20:54
【摘要】：功率MOSFET器件作为能源管理的核心控制单元,由于具有良好的电学特性和低廉的成本,因而广泛应用在汽车电子、消费电子以及航空航天等领域。目前在高端市场的应用领域里,国外的半导体公司仍然占据主导,国内的VDMOS设计与制造技术处于落后地位,特别是器件的雪崩耐量低、可靠性差等问题。虽然国内外对于雪崩耐量的理论研究已经比较成熟,但是提出一种架构合理、生产成本低廉的雪崩耐量加固方案依然非常困难。本论文是基于本实验小组与国内某著名半导体制造商的合作课题,主要目的是研发一款具有高雪崩耐量的600V平面栅VDMOS器件,籍此推动高性能VDMOS的国产化。本论文的主要内容如下:首先介绍了VDMOS器件设计的理论基础和雪崩耐量的加固方法。接着研究不同器件的结构与特点,选取合适的元胞和终端结构,并根据实际工艺提出VDMOS器件可行的工艺流程方案。基于Tsuprem4/Medici仿真软件,通过优化工艺条件以及元胞尺寸,得到基本的元胞参数设计,针对影响雪崩耐量的关键因素,并提出H型N~+接触孔的版图设计方案,进一步提升器件的雪崩耐量。接着进行VDMOS器件终端的仿真优化设计。首先选取JTE终端结构,利用软件Tsuprem4/Medici,仿真得到峰值电场小于2×10~5 V/cm,耐压大小满足设计规范的结果。接着采用先进的高温推阱工艺,设计了VLD终端结构,仿真得到峰值电场小于1.8×10~5 V/cm、击穿稳定性更好的结果。最后利用Candence软件完成版图绘制,成功流片。对流片样品的静态参数和雪崩电流进行测试,第一次流片结果表明,击穿电压大于640V,阈值为3V,导通电阻为1.75Ω,雪崩耐量低于0.1A。其后更改了工艺流程,并且重新流片,第二次流片测试结果表明,两种元胞结构的雪崩电流分别为2.1A、2.5A,可知通过改进版图和工艺设计,雪崩耐量能得到显著提高。
[Abstract]:As the core control unit of energy management, power MOSFET devices are widely used in automotive electronics, consumer electronics, aerospace and other fields because of their good electrical properties and low cost. At present, in the application field of high-end market, foreign semiconductor companies still dominate, and domestic VDMOS design and manufacturing technology is in a backward position, especially the problems of low avalanche tolerance and poor reliability of devices. Although the theoretical research on avalanche tolerance has been mature at home and abroad, it is still very difficult to propose an avalanche tolerance reinforcement scheme with reasonable structure and low production cost. This paper is based on the research work of this experiment group and a famous semiconductor manufacturer in China. The main purpose of this paper is to develop a 600V planar gate VDMOS device with high avalanche tolerance to promote the localization of high performance VDMOS. The main contents of this thesis are as follows: firstly, the theoretical basis of VDMOS device design and the strengthening method of avalanche tolerance are introduced. Then, the structure and characteristics of different devices are studied, and the appropriate cellular and terminal structures are selected, and the feasible technological process of VDMOS devices is put forward according to the actual process. Based on Tsuprem4/Medici simulation software, the basic cell parameter design is obtained by optimizing the process conditions and cell size. Aiming at the key factors affecting the avalanche tolerance, the layout design scheme of H type N- contact hole is proposed. Further improve the avalanche tolerance of the device. Then the simulation optimization design of VDMOS device terminal is carried out. Firstly, the JTE terminal structure is selected, and the peak electric field is less than 2 脳 10 ~ 5 V / cm by software Tsuprem4/Medici, simulation. Then the VLD terminal structure is designed by using advanced high-temperature push-well technology. The simulation results show that the peak electric field is less than 1.8 脳 10 ~ (5) V / cm, and the breakdown stability is better. Finally, using Candence software to complete the layout drawing, successful flow. The static parameters and avalanche current of the sample were measured. The results of the first flowsheet show that the breakdown voltage is greater than 640 V, the threshold is 3 V, the on-resistance is 1.75 惟, and the avalanche tolerance is less than 0.1 A. Then the technological process was changed and the flow sheet was reflow. The results of the second flowsheet test showed that the avalanche current of the two cellular structures was 2.1A ~ (2. 5) A, respectively. It can be seen that the avalanche tolerance can be improved significantly by improving the layout and the technological design.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386
本文编号：2294812
[Abstract]:As the core control unit of energy management, power MOSFET devices are widely used in automotive electronics, consumer electronics, aerospace and other fields because of their good electrical properties and low cost. At present, in the application field of high-end market, foreign semiconductor companies still dominate, and domestic VDMOS design and manufacturing technology is in a backward position, especially the problems of low avalanche tolerance and poor reliability of devices. Although the theoretical research on avalanche tolerance has been mature at home and abroad, it is still very difficult to propose an avalanche tolerance reinforcement scheme with reasonable structure and low production cost. This paper is based on the research work of this experiment group and a famous semiconductor manufacturer in China. The main purpose of this paper is to develop a 600V planar gate VDMOS device with high avalanche tolerance to promote the localization of high performance VDMOS. The main contents of this thesis are as follows: firstly, the theoretical basis of VDMOS device design and the strengthening method of avalanche tolerance are introduced. Then, the structure and characteristics of different devices are studied, and the appropriate cellular and terminal structures are selected, and the feasible technological process of VDMOS devices is put forward according to the actual process. Based on Tsuprem4/Medici simulation software, the basic cell parameter design is obtained by optimizing the process conditions and cell size. Aiming at the key factors affecting the avalanche tolerance, the layout design scheme of H type N- contact hole is proposed. Further improve the avalanche tolerance of the device. Then the simulation optimization design of VDMOS device terminal is carried out. Firstly, the JTE terminal structure is selected, and the peak electric field is less than 2 脳 10 ~ 5 V / cm by software Tsuprem4/Medici, simulation. Then the VLD terminal structure is designed by using advanced high-temperature push-well technology. The simulation results show that the peak electric field is less than 1.8 脳 10 ~ (5) V / cm, and the breakdown stability is better. Finally, using Candence software to complete the layout drawing, successful flow. The static parameters and avalanche current of the sample were measured. The results of the first flowsheet show that the breakdown voltage is greater than 640 V, the threshold is 3 V, the on-resistance is 1.75 惟, and the avalanche tolerance is less than 0.1 A. Then the technological process was changed and the flow sheet was reflow. The results of the second flowsheet test showed that the avalanche current of the two cellular structures was 2.1A ~ (2. 5) A, respectively. It can be seen that the avalanche tolerance can be improved significantly by improving the layout and the technological design.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386
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