高速ADC的输入输出接口电路设计

发布时间：2018-11-04 09:51

【摘要】：随着电子系统的工作频率越来越高,无线通信、雷达、软件无线电等应用正在不断地推动前端的A/D转换器向射频端靠拢,ADC的性能已经成为制约整机性能提升的瓶颈,这其中的输入输出接口技术又是设计高性能ADC的重要环节,成为了研究的热点。论文首先,分析介绍了输入信号完整性问题,围绕其中的反射、串扰、信号抖动、EMI噪声以及高频信号的损耗等影响因素,分析了其形成原因并从电路模块设计、器件尺寸大小、布局布线等方面给出了相应的解决方案。其次,分析了输入接口设计中需要考虑的因素,并据此开展了相应的设计,这些因素包括输入阻抗、输入驱动电平、带宽和通带平坦度、信噪比和失真等。为应对输入信号完整性问题,设计了输入阻抗匹配电路,包括其中的数字控制模块、开关网络、比较器等电路,实现了电阻的精准匹配,减小了信号的反射;为提高信号的线性度和带宽,设计了输入缓冲级电路,实现了信号的高速传输。论文基于TSMC 0.18μm CMOS工艺,利用Cadence Spectre进行电路设计和仿真。仿真结果表明:阻抗匹配电路可将电阻阻值稳定在100Ω±1.43%;输入缓冲级电路的SFDR为86.90dB,带宽可达到3.6GHz,均达到设计要求。然后,分析了输出接口电路的发展,并基于LVDS技术开展输出接口电路的设计,包括驱动电路、共模反馈电路、基准电路和缓冲电路等,设计时考虑了功耗、面积、性能等多方面因素,增加了预充放电技术、负反馈钳位技术以及偏斜调整技术等等。论文对设计的输出接口电路进行了仿真,仿真结果表明,在输入信号为1GHz的速率、电源电压为1.8V的工作条件下,LVDS输出信号稳定在共模电平上下300mV左右,且占空比达到48%,满足设计要求。最后,根据版图设计规则,分析了设计过程中可能遇到的一些问题,如串扰、噪声、匹配以及闩锁效应和天线效应等,并给出了相应的解决方案,完成了 LVDS输出接口电路版图的设计与验证。
[Abstract]:With the increasing frequency of electronic system, wireless communication, radar, software radio and other applications are constantly promoting the front end of the A / D converter to the RF end, the performance of ADC has become a bottleneck restricting the performance of the whole machine. The input-output interface technology is an important part of designing high-performance ADC and has become a hot research topic. First of all, the paper introduces the integrity of input signal, including reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal, analyzes the reasons of its formation, and designs the circuit module from the point of view of the reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal. The corresponding solutions are given in terms of device size, layout and wiring. Secondly, the factors that need to be considered in the design of the input interface are analyzed, and the corresponding design is carried out. These factors include input impedance, input driving level, bandwidth and passband flatness, signal-to-noise ratio and distortion and so on. In order to deal with the problem of input signal integrity, the input impedance matching circuit is designed, including digital control module, switch network, comparator and so on, which realizes the accurate matching of resistance and reduces the reflection of signal. In order to improve the linearity and bandwidth of the signal, the input buffer level circuit is designed, and the high-speed transmission of the signal is realized. Based on TSMC 0.18 渭 m CMOS process, the circuit is designed and simulated by Cadence Spectre. The simulation results show that the impedance matching circuit can stabilize the resistance value to 100 惟卤1.43 and the SFDR of the input buffer circuit is 86.90 dB, and the bandwidth can reach 3.6 GHz, all of which meet the design requirements. Then, the development of output interface circuit is analyzed, and the design of output interface circuit based on LVDS technology is carried out, including drive circuit, common-mode feedback circuit, reference circuit and buffer circuit. Many factors, such as performance, precharge and discharge technology, negative feedback clamp technology and skew adjustment technology are added. The output interface circuit is simulated in this paper. The simulation results show that under the condition that the input signal is 1GHz and the power supply voltage is 1.8 V, the output signal of LVDS is stable at the common mode level about 300mV. And duty cycle up to 48, meet the design requirements. Finally, according to the layout design rules, some possible problems in the design process, such as crosstalk, noise, matching, latch effect and antenna effect, are analyzed, and the corresponding solutions are given. The layout of LVDS output interface circuit is designed and verified.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

【参考文献】