4GSPS任意波形发生器数据产生模块设计
发布时间：2018-11-08 11:17
【摘要】：任意波形发生器基于直接数字合成技术,是近年来发展迅速的一类信号源。凭借其输出频率分辨率高、频率稳定性强、能输出用户自定义复杂波形等优势,任意波形发生器被广泛应用于电子测试领域中。随着电子技术的发展,测试任务中对激励信号源的频率带宽、波形复杂度都提出了更高的要求。对任意波形发生器而言,采样率和波形存储深度是最基础也是最重要的两个参数,这两个参数决定了仪器输出波形的质量。如何提高采样率以及存储深度,成为任意波形发生器研究中的热点和难点。针对上述背景,本文主要讨论任意波形发生器中数据产生模块的设计。该设计基于“4GSPS任意波形发生器”项目,功能是将所需生成波形数据进行存储,并在波形合成过程中对波形数据进行高速寻址输出,是直接决定任意波形发生器采样率和存储深度指标的关键设计。为实现设计目标,本文具体完成的工作如下:1.高速深存储波形查找表设计。根据模块的指标要求,论证了将DDR3 SDRAM作为波形查找表的可行性,重点分析了DDR3 SDRAM波形数据不连续以及读取效率不稳定的问题,并分别给出数据缓存方案以及高效读取数据方法。最终在FPGA中完成数据跨时钟域缓存、高速存储器接口等逻辑设计,使波形数据产生模块达到最高4GSPS采样率数据产生速度,以及2G点的存储深度要求。2.针对在生成复杂长周期信号时,波形存储空间的利用效率低下的问题,分析了序列合成方法的原理和设计方案。结合DDR3 SDRAM的寻址特点,提出了一种基于指令方式的序列波地址发生器设计,该地址发生器具备灵活快速地对波形地址进行触发、循环和跳转等操作的能力,可以实现最大波形段长度64M点,段重复次数为1到616?10次的序列波形的合成输出。3.测试和验证。针对相应功能和参数指标,制定测试方案并搭建测试平台,通过对测试结果的分析,验证模块能以最高4GSPS采样率产生各类常规波、任意波,并且实现了指定参数的触发以及序列合成功能。
[Abstract]:Arbitrary waveform generator based on direct digital synthesis technology is a kind of signal source developed rapidly in recent years. With the advantages of high frequency resolution, strong frequency stability and the ability to output user-defined complex waveforms, arbitrary waveform generators are widely used in the field of electronic testing. With the development of electronic technology, the frequency bandwidth and waveform complexity of excitation signal source are required higher in the test task. For arbitrary waveform generator, sampling rate and waveform storage depth are the two most basic and important parameters, which determine the quality of the output waveform of the instrument. How to improve the sampling rate and storage depth has become a hot and difficult point in the research of arbitrary waveform generator. In view of the above background, this paper mainly discusses the design of data generation module in arbitrary waveform generator. The design is based on "4GSPS arbitrary Waveform Generator" project. The function of this design is to store the generated waveform data and to output the waveform data at high speed in the waveform synthesis process. It is a key design that directly determines the sampling rate and storage depth of arbitrary waveform generator. In order to achieve the design goal, the work accomplished in this paper is as follows: 1. High speed deep storage waveform lookup table design. According to the requirements of the module, the feasibility of using DDR3 SDRAM as a waveform lookup table is demonstrated. The problems of DDR3 SDRAM waveform data discontinuity and unstable reading efficiency are analyzed, and the data cache scheme and efficient data reading method are given respectively. Finally, the data across clock domain cache and high-speed memory interface are designed in FPGA to make the waveform data generation module achieve the maximum 4GSPS sampling rate data generation speed and the storage depth of 2G points. 2. Aiming at the inefficient use of waveform storage space in generating complex long-period signals, the principle and design scheme of sequence synthesis method are analyzed. According to the addressing characteristics of DDR3 SDRAM, a design of sequential wave address generator based on instruction is proposed. The address generator has the ability to trigger, cycle and jump the waveform address flexibly and quickly. The synthetic output of the sequence waveform with the maximum waveform length of 64m and the number of repeats of the segment between 1 and 616 ~ 10 times can be realized. 3. Test and verify. According to the corresponding function and parameter index, the test scheme is established and the test platform is built. Through the analysis of the test results, it is proved that the module can produce all kinds of conventional waves and arbitrary waves at the highest 4GSPS sampling rate. The trigger of specified parameters and the function of sequence synthesis are realized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN741
本文编号：2318325
[Abstract]:Arbitrary waveform generator based on direct digital synthesis technology is a kind of signal source developed rapidly in recent years. With the advantages of high frequency resolution, strong frequency stability and the ability to output user-defined complex waveforms, arbitrary waveform generators are widely used in the field of electronic testing. With the development of electronic technology, the frequency bandwidth and waveform complexity of excitation signal source are required higher in the test task. For arbitrary waveform generator, sampling rate and waveform storage depth are the two most basic and important parameters, which determine the quality of the output waveform of the instrument. How to improve the sampling rate and storage depth has become a hot and difficult point in the research of arbitrary waveform generator. In view of the above background, this paper mainly discusses the design of data generation module in arbitrary waveform generator. The design is based on "4GSPS arbitrary Waveform Generator" project. The function of this design is to store the generated waveform data and to output the waveform data at high speed in the waveform synthesis process. It is a key design that directly determines the sampling rate and storage depth of arbitrary waveform generator. In order to achieve the design goal, the work accomplished in this paper is as follows: 1. High speed deep storage waveform lookup table design. According to the requirements of the module, the feasibility of using DDR3 SDRAM as a waveform lookup table is demonstrated. The problems of DDR3 SDRAM waveform data discontinuity and unstable reading efficiency are analyzed, and the data cache scheme and efficient data reading method are given respectively. Finally, the data across clock domain cache and high-speed memory interface are designed in FPGA to make the waveform data generation module achieve the maximum 4GSPS sampling rate data generation speed and the storage depth of 2G points. 2. Aiming at the inefficient use of waveform storage space in generating complex long-period signals, the principle and design scheme of sequence synthesis method are analyzed. According to the addressing characteristics of DDR3 SDRAM, a design of sequential wave address generator based on instruction is proposed. The address generator has the ability to trigger, cycle and jump the waveform address flexibly and quickly. The synthetic output of the sequence waveform with the maximum waveform length of 64m and the number of repeats of the segment between 1 and 616 ~ 10 times can be realized. 3. Test and verify. According to the corresponding function and parameter index, the test scheme is established and the test platform is built. Through the analysis of the test results, it is proved that the module can produce all kinds of conventional waves and arbitrary waves at the highest 4GSPS sampling rate. The trigger of specified parameters and the function of sequence synthesis are realized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN741
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