基于抗随机性故障分析的高效率可测试设计方法
发布时间：2018-11-11 09:56
【摘要】：为了在提高芯片测试覆盖率的同时减少生产测试时的测试向量,提出了一种基于对电路进行抗随机向量故障分析,进而在电路中插入测试点,从而提供芯片的测试效率的方法。实际电路的实验结果表明,使用了该方法的可测性设计,在不损失测试覆盖率的情况下,能够有效地减少平均45.85%的测试向量,从而帮助设计者提高芯片的测试效率。
[Abstract]:In order to improve the test coverage and reduce the test vector in production, a method of anti-random vector fault analysis based on the circuit is proposed, and then the test point is inserted into the circuit, thus providing the test efficiency of the chip. The experimental results of the practical circuit show that the testability design of this method can effectively reduce the average test vector by 45.85% without losing the test coverage, thus helping the designer to improve the testing efficiency of the chip.
【作者单位】： 格罗方德半导体科技(上海)有限公司;
【分类号】：TN407
本文编号：2324494
[Abstract]:In order to improve the test coverage and reduce the test vector in production, a method of anti-random vector fault analysis based on the circuit is proposed, and then the test point is inserted into the circuit, thus providing the test efficiency of the chip. The experimental results of the practical circuit show that the testability design of this method can effectively reduce the average test vector by 45.85% without losing the test coverage, thus helping the designer to improve the testing efficiency of the chip.
【作者单位】： 格罗方德半导体科技(上海)有限公司;
【分类号】：TN407
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1 邵正隆;面向复用的软件测试设计模型的研究与实现[D];清华大学;2006年
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