10位10M采样率逐次逼近模数转换器设计
发布时间：2018-11-13 09:46
【摘要】：逐次逼近模数转换器(ADC)具有中等转换速度和中等转换精度,采用CMOS工艺实现可以保证较小的芯片面积和低功耗,而且便于实现多路转换,在功耗、精度、速度和成本方面具有综合优势,被广泛应用于无线通信、工业控制、医疗仪器以及微处理器辅助模数转换接口等领域。本文设计了一个精度为10bit,速度为10Ms/s的低功耗逐次逼近ADC。电路采用差分输入,同步时钟,并具有省电模式。工作在完成ADC电路设计仿真的基础上,完成了整个电路的物理版图设计及后仿真。该逐次逼近ADC采用GSMC 0.18um混合信号CMOS工艺设计,芯片面积为0.8mm×0.8mm。版图后防真结果显示,在10Ms/s下,其SNDR为59.38dB,即ENOB为9.57位,
[Abstract]:The successive approximation analog-to-digital converter (ADC) has medium conversion speed and medium conversion precision. Using CMOS technology can guarantee small chip area and low power consumption, and it is easy to realize multiplexing, power consumption and precision. The advantages of speed and cost are widely used in wireless communication, industrial control, medical instruments and microprocessor aided A / D conversion interface and so on. In this paper, a low power successive approximation ADC. with an accuracy of 10 bits and a speed of 10Ms/s is designed. The circuit uses differential input, synchronous clock and power saving mode. On the basis of ADC circuit design and simulation, the physical layout design and post simulation of the whole circuit are completed. The successive approximation ADC is designed by GSMC 0.18um mixed signal CMOS process. The chip area is 0.8mm 脳 0.8mm. The result shows that under 10Ms/s, its SNDR is 59.38 dB, that is, ENOB is 9.57 bits.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792
[Abstract]:The successive approximation analog-to-digital converter (ADC) has medium conversion speed and medium conversion precision. Using CMOS technology can guarantee small chip area and low power consumption, and it is easy to realize multiplexing, power consumption and precision. The advantages of speed and cost are widely used in wireless communication, industrial control, medical instruments and microprocessor aided A / D conversion interface and so on. In this paper, a low power successive approximation ADC. with an accuracy of 10 bits and a speed of 10Ms/s is designed. The circuit uses differential input, synchronous clock and power saving mode. On the basis of ADC circuit design and simulation, the physical layout design and post simulation of the whole circuit are completed. The successive approximation ADC is designed by GSMC 0.18um mixed signal CMOS process. The chip area is 0.8mm 脳 0.8mm. The result shows that under 10Ms/s, its SNDR is 59.38 dB, that is, ENOB is 9.57 bits.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792
【参考文献】
相关期刊论文 前10条
1 万鑫;谈熙;;一种非二进制权重的高能效比逐次比较型模数转换器[J];固体电子学研究与进展;2013年04期
2 刘洋;蔡啸;;简述选择模数转换器时的技术指标与注意事项[J];河南科技;2013年10期
3 陈铖颖;黑勇;胡晓宇;;一种轨至轨10位逐次逼近模数转换器的设计[J];微电子学;2012年05期
4 范修宏;颜t，
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