基于纳米器件构建的CMOS逻辑电路设计研究

发布时间：2018-11-13 14:29

【摘要】：本文利用非平衡格林函数和泊松方程建立了碳纳米管场效应管(CNTFET)的计算模型,自洽求解基于新型结构CNTFET的输运特性。在器件电学特性研究基础上,利用Verilog-A建立查找表模型,在HSPICE中构建电子电路,以研究不同结构CNTFET对电路性能的影响。另外,研究随器件尺寸缩小、栅极氧化层进一步变薄而导致栅极电流隧穿效应,以及栅极隧穿电流对电路逻辑功能的影响。本文主要内容包括以下几个部分:(1)本文提出了一种单Halo掺杂结构CNTFET(SH-CNTFET),并和普通结构的场效应管(C-CNTFET)进行了比较,表明前者有更好的射频和开关特性。电路级别仿真结果表明,基于SH-CNTFET的反相器有更好的性能;此外,我们还分别探讨了基于SH-CNTFET和C-CNTFET的6管静态随机存储器(6T SRAM)的性能,结果表明基于SH-CNTFET的SRAM单元有更大的静态噪声容限(SNM),更小的写功耗及功耗延迟积(PDP),并求解出Halo掺杂浓度的最优值。(2)本文提出了一种异质轻掺杂隧穿型场效应管(LD-HTFET),并和普通高K、异质隧穿场效应管进行比较,异质结构能够减小器件的栅电容,轻掺杂能够有效提高开关电流比,从而使得该结构具有较好的静态特性和高频特性。探讨了供电电压对隧穿场效应管构建的反相器电路性能的影响。结果表明,基于LD-HTFET的反相器电路有更低的功耗、更大的静态噪声容限和增益。(3)本文首先研究栅电流形成机制,并建立栅电流器件模型。其次,基于二输入与门,探讨了当器件尺寸进一步减小时,同样利用查找表加入栅极隧穿电流,考虑栅极隧穿电流对电路逻辑功能的影响。结果表明,当器件氧化层厚度为0.5nm时,栅极隧穿效应会使得电路逻辑功能出错。
[Abstract]:In this paper, a computational model of carbon nanotube field effect tube (CNTFET) is established by using nonequilibrium Green's function and Poisson's equation. The transport characteristics based on new structure CNTFET are solved by self-consistent method. Based on the study of the electrical characteristics of the devices, the look-up table model is established by using Verilog-A, and the electronic circuit is constructed in HSPICE to study the influence of different CNTFET structures on the circuit performance. In addition, the gate current tunneling effect and the effect of gate tunneling current on the logic function of the circuit are studied as the gate oxide layer becomes thinner with the reduction of the device size. The main contents of this paper are as follows: (1) A single Halo doped CNTFET (SH-CNTFET) structure is proposed and compared with the field effect transistor (C-CNTFET) of common structure. It shows that the former has better RF and switching characteristics. The circuit level simulation results show that the inverter based on SH-CNTFET has better performance. In addition, we also discuss the performance of 6-transistor static random access memory (6T SRAM) based on SH-CNTFET and C-CNTFET, respectively. The results show that the SRAM cell based on SH-CNTFET has more static noise tolerance (SNM),. Lower write power and power delay product (PDP), and get the optimal value of Halo doping concentration. (2) in this paper, we propose a heterostructure light-doped tunneling field-effect transistor (LD-HTFET), and compare with ordinary high K, Compared with the heterojunction tunneling FET, the heterostructure can reduce the gate capacitance of the device, and the light doping can effectively improve the switching current ratio, which makes the structure have better static and high frequency characteristics. The effect of power supply voltage on the performance of the inverter constructed by tunneling FET is discussed. The results show that the inverter circuit based on LD-HTFET has lower power consumption, greater static noise tolerance and gain. (3) in this paper, the generation mechanism of gate current is studied firstly, and the gate current device model is established. Secondly, on the basis of two-input and gate, when the device size is further reduced, the gate tunneling current is also added to the lookup table, and the influence of the gate tunneling current on the logic function of the circuit is considered. The results show that when the oxide layer thickness of the device is 0.5nm, the gate tunneling effect will make the circuit logic function go wrong.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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