基于电荷平衡的超结LDMOS仿真和工艺设计
发布时间：2018-11-20 09:35
【摘要】：人们现在的生活与娱乐经常伴随着手机、电脑、平板等电子产品。在任何电子产品中,电源是必不可少的组成部分,而功率半导体器件是对电源电流和电压处理的必要单元。功率半导体器件经过六十多年的发展,已经形成了一个庞大的家族。新的家族成员凭借其自身优良的电学特性不断侵蚀着原先成员的应用市场。功率半导体器件中,MOS器件没有自热效应,不会发生二次击穿,为电压控制型器件,其驱动电路简单。这些优点使其得到了广泛的应用。在功率MOS器件设计中,击穿电压与比导通电阻的对立关系很严峻。为了解决这一矛盾,超结结构提了出来。该结构不仅有着电学特性优良的特点同时还有着很好的技术转移特性。这些优点使其被称为“功率器件发展史上的里程碑”。近几年来,超结结构的应用和优化的研究十分热门。纵向超结结构的优势很大,拥有良好的电学特性,目前主要对其制作工艺进行开发。横向超结结构虽然存在衬底辅助耗尽效应,影响了其应用,但是纵向超结结构的成功,使人们看到了横向超结结构的巨大潜力,从而出现了多种多样对其优化的结构和技术。本文在前人工作的基础上,从电荷平衡的角度消除衬底辅助耗尽效应,提出了两种新型的器件结构,利用仿真软件ISE TCAD 10.0对两种器件结构进行设计优化和电学特性的仿真分析。两种新型的器件分别为DNU SJ-LDMOS(具有N柱分区非平衡SJ-LDMOS)和NBB SJ-LDMOS(具有N型埋层Buffer SJ-LDMOS)。通过仿真,在相同参数的条件下,对DNU SJ-LDMOS与平衡SJ-LDMOS进行了电学特性对比。DNU SJ-LDMOS比SJ-LDMOS的比导通电阻降低14.08%,击穿电压提高38.74%。对DNU SJ-LDMOS的分区浓度,分区长度,分区个数等影响器件电学特性的参数进行优化设计,可以得到器件的比导通电阻为46.99mΩ?cm2,击穿电压为207.0V。同样,在相同参数的条件下,对NBB SJ-LDMOS、传统SJ-LDMOS和Buffer SJ-LDMOS进行了电学特性对比。对比于传统SJ-LDMOS,Buffer SJ-LDMOS和NBB SJ-LDMOS依次降低比导通电阻27.8%,38.1%,击穿电压分别提高11.7%、62.6%。对比于Buffer SJ-LDMOS,NBB SJ-LDMOS降低比导通电阻21.8%,击穿电压提高了45.5%。对NBB SJ-LDMOS的N埋层浓度,N埋层厚度,N埋层长度等影响器件电学特性的参数进行优化设计,可以得到器件的比导通电阻为82.38mΩ?cm2,击穿电压为322.8V。最后本文介绍了功率器件的BCD工艺以及传统SJ-LDMOS的工艺流程,开发了DNU SJ-LDMOS和NBB SJ-LDMOS的工艺流程,同时设计了工艺中所用的版图。
[Abstract]:People's life and entertainment are often accompanied by mobile phones, computers, tablets and other electronic products. In any electronic product, power supply is an essential component, and power semiconductor devices are necessary units for power supply current and voltage processing. After more than 60 years of development, power semiconductor devices have formed a large family. The new members of the family continue to erode the application market of the original members by virtue of their own excellent electrical properties. In the power semiconductor devices, the MOS device has no self-heating effect and no secondary breakdown. It is a voltage-controlled device and its driving circuit is simple. These advantages make it widely used. In the design of power MOS devices, the relationship between breakdown voltage and specific on-resistance is very severe. In order to solve this contradiction, the superjunction structure was proposed. The structure has not only excellent electrical properties but also good technology transfer characteristics. These advantages make it known as a milestone in the history of power device development. In recent years, the application and optimization of superjunction structures are very popular. The longitudinal superjunction structure has great advantages and good electrical properties. At present, its fabrication process is mainly developed. Although there exists substrate-assisted depletion effect in transverse superjunction structures, the success of longitudinal superjunction structures makes people see the great potential of transverse superjunction structures, thus various structures and techniques for their optimization have emerged. In this paper, based on the previous work, two novel device structures are proposed to eliminate the substrate-assisted depletion effect from the angle of charge balance. The simulation software ISE TCAD 10.0 is used to optimize the design of the two devices and to analyze the electrical characteristics. The two novel devices are DNU SJ-LDMOS (with N-column nonequilibrium SJ-LDMOS) and NBB SJ-LDMOS (with N-type buried Buffer SJ-LDMOS). Through simulation, the electrical characteristics of DNU SJ-LDMOS and balanced SJ-LDMOS are compared under the same parameters. The specific on-resistance of DNU SJ-LDMOS is 14.08 lower than that of SJ-LDMOS, and the breakdown voltage is increased 38.74. By optimizing the design of the parameters which affect the electrical properties of DNU SJ-LDMOS, such as the concentration, length and number of zones, the specific on-resistance of the device is 46.99m 惟? cm2, breakdown voltage is 207.0V. The electrical properties of NBB SJ-LDMOS, traditional SJ-LDMOS and Buffer SJ-LDMOS are also compared under the same parameters. Compared with the conventional SJ-LDMOS,Buffer SJ-LDMOS and NBB SJ-LDMOS, the specific on-resistance of 27.8% and 38.1% were decreased in turn, and the breakdown voltage was increased by 11.7% and 62.6%, respectively. Compared with Buffer SJ-LDMOS,NBB SJ-LDMOS, the breakdown voltage increased by 45.5%. The parameters affecting the electrical properties of NBB SJ-LDMOS, such as N buried layer concentration, N buried layer thickness and N buried layer length, are optimized. The specific on-resistance of the device is 82.38 m 惟? cm2, breakdown voltage is 322.8V. Finally, this paper introduces the BCD process of power device and the process flow of traditional SJ-LDMOS, develops the process flow of DNU SJ-LDMOS and NBB SJ-LDMOS, and designs the layout used in the process.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
本文编号：2344548
[Abstract]:People's life and entertainment are often accompanied by mobile phones, computers, tablets and other electronic products. In any electronic product, power supply is an essential component, and power semiconductor devices are necessary units for power supply current and voltage processing. After more than 60 years of development, power semiconductor devices have formed a large family. The new members of the family continue to erode the application market of the original members by virtue of their own excellent electrical properties. In the power semiconductor devices, the MOS device has no self-heating effect and no secondary breakdown. It is a voltage-controlled device and its driving circuit is simple. These advantages make it widely used. In the design of power MOS devices, the relationship between breakdown voltage and specific on-resistance is very severe. In order to solve this contradiction, the superjunction structure was proposed. The structure has not only excellent electrical properties but also good technology transfer characteristics. These advantages make it known as a milestone in the history of power device development. In recent years, the application and optimization of superjunction structures are very popular. The longitudinal superjunction structure has great advantages and good electrical properties. At present, its fabrication process is mainly developed. Although there exists substrate-assisted depletion effect in transverse superjunction structures, the success of longitudinal superjunction structures makes people see the great potential of transverse superjunction structures, thus various structures and techniques for their optimization have emerged. In this paper, based on the previous work, two novel device structures are proposed to eliminate the substrate-assisted depletion effect from the angle of charge balance. The simulation software ISE TCAD 10.0 is used to optimize the design of the two devices and to analyze the electrical characteristics. The two novel devices are DNU SJ-LDMOS (with N-column nonequilibrium SJ-LDMOS) and NBB SJ-LDMOS (with N-type buried Buffer SJ-LDMOS). Through simulation, the electrical characteristics of DNU SJ-LDMOS and balanced SJ-LDMOS are compared under the same parameters. The specific on-resistance of DNU SJ-LDMOS is 14.08 lower than that of SJ-LDMOS, and the breakdown voltage is increased 38.74. By optimizing the design of the parameters which affect the electrical properties of DNU SJ-LDMOS, such as the concentration, length and number of zones, the specific on-resistance of the device is 46.99m 惟? cm2, breakdown voltage is 207.0V. The electrical properties of NBB SJ-LDMOS, traditional SJ-LDMOS and Buffer SJ-LDMOS are also compared under the same parameters. Compared with the conventional SJ-LDMOS,Buffer SJ-LDMOS and NBB SJ-LDMOS, the specific on-resistance of 27.8% and 38.1% were decreased in turn, and the breakdown voltage was increased by 11.7% and 62.6%, respectively. Compared with Buffer SJ-LDMOS,NBB SJ-LDMOS, the breakdown voltage increased by 45.5%. The parameters affecting the electrical properties of NBB SJ-LDMOS, such as N buried layer concentration, N buried layer thickness and N buried layer length, are optimized. The specific on-resistance of the device is 82.38 m 惟? cm2, breakdown voltage is 322.8V. Finally, this paper introduces the BCD process of power device and the process flow of traditional SJ-LDMOS, develops the process flow of DNU SJ-LDMOS and NBB SJ-LDMOS, and designs the layout used in the process.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
【参考文献】
相关期刊论文 前2条
1 黄示;郭宇锋;姚佳飞;夏晓娟;徐跃;张瑛;;横向超结器件衬底辅助耗尽效应的研究与展望[J];微电子学;2013年04期
2 陈星弼;;超结器件[J];电力电子技术;2008年12期
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