基于SystemC的1553B总线事务级模型设计
发布时间：2018-11-21 12:04
【摘要】：随着集成电路规模的不断增大,电路性能提升的同时也给设计和验证工作带来了新的挑战。在传统的超大规模集成电路的设计流程中,硬件的设计与软件的设计工作是分开进行的,并且软件的设计往往要滞后于硬件,在整合软硬件时如果想要对设计进行修改又不得不重新划分软硬件的职能,并从头开始设计。这就带来了时间和精力上的浪费。对于验证而言,使用传统高级语言的验证程序与周期精确的硬件描述语言进行混合仿真,速度很慢,往往会导致整个进度的滞后。这在追求产品快速更新抢占市场的今天是难以忍受的。为了解决以上的问题,可以在设计流程中使用System C语言先进行系统级的设计,软硬件的设计工作可以同步进行。各个单元采用事务级的建模方法,设计周期更短并且仿真速度比传统的RTL模型快2~3个数量级,通过验证后再将软硬件翻译成对应的高级语言和硬件描述语言,从而达到节约时间的目的。本文设计的1553B总线事务级模型是实验室事务级So C验证平台的一部分,可以对基于1553B总线的IP核完成快速的验证工作。采用System C语言进行事务级的建模,建模标准采用的是TLM2.0,模块之间的通讯更加规范。首先介绍1553B总线的应用背景、发展现状以及对其进行建模的必要性,利用System C进行事务级建模的机制,接着提出了1553B总线模型的整体设计方案,完成总线控制器接口(BC接口)、远程终端接口(RT接口)和事务级总线通道的设计工作。在总线模型的各个部分设计工作完成后,为其搭建测试平台并提出两种测试方案,一是对其功能点进行点对点的测试,验证功能的正确性,二是采用对1553B总线16bit指令字进行穷举的方式对总线模型进行全覆盖测试,评估模型的仿真速度。通过初步的测试后将该事务级总线模型挂载到LEON3 So C验证平台上进行最终的测试,并在1553B总线模型的RT端挂载一个真实的IP——DES密码算法模块,完成总线模型的验证工作。经验证该1553B总线事务级模型功能实现正确,成功完成了与So C验证平台的通信,并且相比于传统的RTL模型提高了仿真速度,可以用于1553B总线IP核的快速验证工作。
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
本文编号：2346913
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
【参考文献】
相关期刊论文 前1条
1 唐豪川;祝永新;;基于SystemC的异构多核通信模块设计[J];微计算机信息;2009年23期
相关博士学位论文 前1条
1 浦汉来;SoC存储子系统系统级性能优化技术研究[D];东南大学;2006年
相关硕士学位论文 前3条
1 冯成;基于FPGA的航电接口板设计[D];南京理工大学;2007年
2 何珍珍;1553B总线接口电路存储器管理控制系统设计[D];西安科技大学;2012年
3 王研;1553B总线现场测试仪的研究及设计[D];西安科技大学;2013年
，本文编号：2346913
本文链接：https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2346913.html
