基于部分簇能量互补逻辑的MRF电路设计
发布时间：2018-11-22 14:21
【摘要】：功耗是电路设计的关键性问题之一,低功耗下的稳定性问题逐渐成为电路设计的热点和挑战,基于马尔科夫随机场(MRF)的低功耗设计从能量的角度出发有效地解决了电路的容错问题,但是其单逻辑的单元结构面积和复杂度制约了该技术在大规模集成电路的应用。该文提出了一种基于部分簇能量的MRF电路设计方法(PMRF),并结合互补逻辑的特点来实现多逻辑结构,面积共享的同时一方面补偿由于部分簇能量带来的性能损失,一方面化简马氏随机场电路设计在较大规模电路设计中的面积和复杂度瓶颈问题。对比传统MRF电路设计,该文用PMRF方法设计了超前进位加法器结构,在低功耗仿真中具有20%的性能提升,并在65 nm TSMC版图实现后取得29%的面积节约和86%的功耗节约。
[Abstract]:Power consumption is one of the key problems in circuit design. The low power design based on Markov random field (MRF) effectively solves the fault tolerance problem of circuits from the point of view of energy. However, the area and complexity of single logic cell structure restrict the application of this technology in large scale integrated circuits (LSI). In this paper, a design method of MRF circuit based on partial cluster energy (PMRF),) is proposed, which combines the characteristics of complementary logic to realize multi-logic structure. On the one hand, area sharing compensates for the loss of performance caused by partial cluster energy. On the one hand, the area and complexity bottleneck of Mahalanobis random field circuit design in large scale circuit design. Compared with traditional MRF circuit design, this paper uses PMRF method to design ahead carry adder structure, which has 20% performance improvement in low power simulation, and achieves 29% area saving and 86% power saving after 65 nm TSMC layout implementation.
【作者单位】： 电子科技大学通信抗干扰国家级重点实验室;
【基金】：国家自然科学基金(61371104)
【分类号】：TN402
，
本文编号：2349623
[Abstract]:Power consumption is one of the key problems in circuit design. The low power design based on Markov random field (MRF) effectively solves the fault tolerance problem of circuits from the point of view of energy. However, the area and complexity of single logic cell structure restrict the application of this technology in large scale integrated circuits (LSI). In this paper, a design method of MRF circuit based on partial cluster energy (PMRF),) is proposed, which combines the characteristics of complementary logic to realize multi-logic structure. On the one hand, area sharing compensates for the loss of performance caused by partial cluster energy. On the one hand, the area and complexity bottleneck of Mahalanobis random field circuit design in large scale circuit design. Compared with traditional MRF circuit design, this paper uses PMRF method to design ahead carry adder structure, which has 20% performance improvement in low power simulation, and achieves 29% area saving and 86% power saving after 65 nm TSMC layout implementation.
【作者单位】： 电子科技大学通信抗干扰国家级重点实验室;
【基金】：国家自然科学基金(61371104)
【分类号】：TN402
，
本文编号：2349623
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