新型纳米场效应管量子效应及其对构建电路影响

发布时间：2018-11-22 17:18

【摘要】：本文采用一种量子力学模型,研究了MOSFET型碳基场效应管的电学特性。该模型基于非平衡格林函数(NEGF)和泊松(Poisson)方程自洽全量子数值解。运用该方法研究了基于不同栅极结构的场效应管的稳态特性。另外,在器件电学特性的基础上,将研究范围扩展至电路,分析了异质结构碳纳米管场效应管(CNTFETs)和石墨烯纳米条带场效应管(GNRFETs)构建电子电路的性能。最后,本文研究了场效应管栅极隧穿电流对逻辑电路功能的影响。本文的主要内容涉及以下三个方面:首先,研究了异质栅结构n-i-n型场效应管以及异质氧化层结构p-i-n型场效应管的电学特性,并与普通结构的场效应管进行比较。结果表明:异质结构尽管增大了器件的迟滞时间,但可以显著提高器件的开关电流比、抑制短沟道效应、减小亚阈摆幅。其次,在器件电学特性的基础上利用Verilog-A建立相应查找表(LUT)模型,在HSPICE中构建电子电路,研究异质结构器件对于电路性能的影响。对于n-i-n型场效应管构建电路,计算了栅金属功函数对功耗,延迟以及功耗-延迟积(PDP)等电路性能的影响,并得出能够减小PDP的优化值;对于p-i-n型场效应管构建的逻辑电路,从栅长、供电电压以及温度三个方面比较了普通结构隧穿场效应管(TFET)、高k-隧穿场效应管(HK-TFET)和异质隧穿场效应管(HTFET)电路稳定性。结果表明,尽管HKTFET构建的逻辑电路具有最小的PDP,但是HTFET构建的逻辑电路的PDP随栅长、温度的变化率最小,即HTFET具有较高的稳定性。最后,探讨了碳基场效应管的栅极隧穿电流对于逻辑电路功能的影响。在碳基场效应管的等效电路模型的基础上利用查找表加入栅极隧穿电流,并构建逻辑电路,研究了场效应管栅极隧穿电流对电路逻辑功能的影响。结果表明,当晶体管栅极氧化层厚度达到0.5nm时,急剧增大的栅极隧穿电流会造成逻辑电路功能错误。
[Abstract]:In this paper, a quantum mechanical model is used to study the electrical properties of MOSFET type carbon based FET. The model is based on the nonequilibrium Green function (NEGF) and Poisson (Poisson) equation. The steady-state characteristics of FET based on different gate structures are studied by using this method. In addition, on the basis of the electrical properties of the device, the research scope is extended to the circuit, and the performance of the heterostructure carbon nanotube field effect tube (CNTFETs) and graphene nanostrip field effect tube (GNRFETs) are analyzed. Finally, the effect of gate tunneling current of FET on the function of logic circuit is studied. The main contents of this paper are as follows: firstly, the electrical properties of heterogate n-i-n FET and heterooxide p-i-n FET are studied. It is compared with the FET with common structure. The results show that the heterostructure increases the hysteresis time of the device, but it can significantly increase the switching current ratio of the device, suppress the short channel effect and reduce the sub-threshold swing amplitude. Secondly, on the basis of the electrical characteristics of the device, the corresponding lookup table (LUT) model is established by using Verilog-A, and the electronic circuit is constructed in the HSPICE, and the influence of the heterostructure device on the circuit performance is studied. For the n-i-n FET circuit, the influence of gate metal work function on power consumption, delay and (PDP) is calculated, and the optimized value of PDP is obtained. For the logic circuit of p-i-n FET, the (TFET), of tunneling FET with common structure is compared from three aspects: gate length, supply voltage and temperature. Stability of high k- tunneling field effect transistor (HK-TFET) and heterostructure tunneling field effect transistor (HTFET) circuits. The results show that although the logic circuit constructed by HKTFET has the smallest PDP, the PDP of the logic circuit constructed by HTFET is the least with the gate length and the rate of temperature change is minimum, that is, the HTFET has higher stability. Finally, the effect of gate tunneling current of carbon based FET on the function of logic circuit is discussed. Based on the equivalent circuit model of carbon based FET, the gate tunneling current is added by lookup table, and the logic circuit is constructed. The effect of FET gate tunneling current on circuit logic function is studied. The results show that when the oxide layer thickness of the transistor gate reaches 0.5nm, the rapidly increasing gate tunneling current will cause the logic circuit function error.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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