QoS片上网络的微电路及架构研究

发布时间：2018-11-24 10:20

【摘要】：伴随着半导体芯片集成工艺的飞速发展,片上系统的研究成果在工业各个领域被广泛的应用。但由于其总线互连结构的局限性,片上网络的概念被研究学者提出来了,国内外众多研究机构也纷纷对这种分布式体系结构进行研究,并且在对芯片面积、功耗消费、网络时延以及吞吐量等方面有特殊需要时的情况下,提出了各式各样的结构模型。本文以多通道专用拓扑网络为基础,以提高网络性能服务质量为目标,对片上网络的关键模块(拓扑网络、死锁避免、缓冲、路由算法、数据拥塞)进行详细的研究。本文先是分析了NoC的国内外研究现状,并对其组成部分、常见的拓扑网络结构、数据交换技术、路由算法、死锁活锁和拓扑网络性能参数等基础理论知识进行阐述,同时也对相关的QoS基础知识进行讲解。本文的数据交换技术是采用包交换技术,路由算法采用XY确定性路由算法,数据包采用交叉阵列开关并行转发,缓存采用虚拟通道技术和FIFO技术。然后提出了改进的多通道专用拓扑网络结构。改进后具有设计简单容易实现、网络直径少、功耗低、数据通路多等优点。具体分析其工作原理和各个组成模块的微电路实现,在此基础上引用弹性缓冲进行流量控制,避免数据拥塞和死锁现象产生。通过弹性缓冲以及虚拟通道的结合运用,业务流能够利用逃跑转发机制避免拥塞,可以进行流量控制而且保证对低优先级数据包的服务质量保证。把每个路由节点中保证QoS的功能部件抽取出来放到共享区域,使高优先级业务流和紧急突发业务流数据包直接转发到共享区域里,得到充足资源后马上转发到目的路由节点,从而达到有效节省硬件消耗和缩小时延的目的。因此通过新型拓扑网络结构、弹性缓冲以及共享区域等关键技术使整个网络达到最佳的QoS性能。最后采用Model sim信号模拟仿真软件对MECS拓扑网络结构微电路进行数据信号模拟,通过NS2网络仿真软件对QoS片上网络的吞吐量、丢失包和网络延迟等性能参数进行仿真,把所得的结果与传统的2Dmesh和Ring进行对比,并用Gnuplot绘制图表。模拟仿真结果发现,本文提出的结构比2Dmesh和Ring具有更大的吞吐量、丢失包较少、平均时延小等优势,缺点是整个体系结构设计复杂度大、物理布线实现难度较高。因此本结构更适用于实时性,交互性的芯片结构。
[Abstract]:With the rapid development of semiconductor chip integration technology, the research results of on-chip system are widely used in various fields of industry. However, due to the limitations of its bus interconnection architecture, the concept of on-chip network has been put forward by researchers, and many domestic and foreign research institutions have also studied this distributed architecture, and in the chip area, power consumption, When the network delay and throughput have special needs, a variety of structural models are proposed. In this paper, the key modules (topology network, deadlock avoidance, buffer, routing algorithm, data congestion) of the on-chip network are studied in detail, based on the multi-channel dedicated topology network and the goal of improving the quality of service of the network. This paper first analyzes the research status of NoC at home and abroad, and describes its components, common topology network structure, data exchange technology, routing algorithm, deadlock lock and topology network performance parameters and other basic theoretical knowledge. At the same time, it also explains the basic knowledge of QoS. In this paper, packet switching technology is used in data exchange, XY deterministic routing algorithm is used in routing algorithm, data packet is forwarded in parallel by cross array switch, virtual channel technology and FIFO technology are used in cache. Then an improved multi-channel dedicated topology structure is proposed. The improved design is simple and easy to implement, the network diameter is small, the power consumption is low, and the data path is many. The working principle and the realization of each component module are analyzed in detail. On this basis, the flexible buffer is used to control the flow, which avoids the phenomenon of data congestion and deadlock. Through the combination of flexible buffer and virtual channel, traffic flow can avoid congestion by using escape forwarding mechanism, which can control traffic and guarantee the quality of service for low-priority packets. The functional components of the guaranteed QoS in each routing node are extracted and put into the shared area, so that the packets of high priority traffic flow and emergency burst traffic flow are forwarded directly to the shared area, and the data packets are forwarded to the destination routing node immediately after the sufficient resources are obtained. In order to achieve the purpose of saving hardware consumption and reducing delay effectively. Therefore, the QoS performance of the whole network is optimized by the key technologies such as new topology network structure, elastic buffer and shared area. Finally, Model sim signal simulation software is used to simulate the data signal of MECS topology microcircuit, and NS2 network simulation software is used to simulate the performance parameters such as throughput, packet loss and network delay on QoS chip. The results are compared with the traditional 2Dmesh and Ring, and the diagrams are drawn with Gnuplot. The simulation results show that the proposed architecture has more throughput, less packet loss and less average delay than 2Dmesh and Ring. The disadvantages of the proposed architecture are the complexity of the architecture design and the difficulty of physical routing. Therefore, the structure is more suitable for real-time, interactive chip structure.
【学位授予单位】：广东工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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