适用于Sigma-Delta ADC的512倍数字抽取滤波器的设计与研究

发布时间：2018-11-29 07:14

【摘要】：Σ-△ADC是集成芯片中非常重要的部分,近几年来对Σ-△ADC的研究更加深入,其应用也是日趋广泛。数字抽取滤波器对Σ-△ADC性能至关重要,结构优化的滤波器能够有效的减少整体设计的面积,降低其功耗。本文首先简单介绍Sigma-Delta ADC,并且重点阐述过采样以及噪声整形两个实现高分辨率的关键技术,同时实现调制器Simulink模型。接着在进行研究分析之后确定本文滤波器的整体结构,并使用MATLAB按照相应指标参数完成各级滤波器的设计与优化。本文所设计的数字滤波器为了实现低功耗、小面积的目标,选择了更具优势的级联结构,包含CIC滤波器、FIR补偿滤波器和半带滤波器,它们分别完成128、2、2的降采样。由于本文调制器为单级的,因此梳状滤波器设计为2级级联递归结构,这样能够有效减小面积以及降低功耗;由于CIC滤波器自身存在一些不利因素,使得我们必须加入一个FIR补偿滤波器来对其进行弥补,也就是实现通带衰减的补偿;同时为了减少运算复杂度,我们分别对FIR补偿滤波器以及半带滤波器系数进行CSD编码。本文在Simulink中实现调制器与滤波器的建模,并对其进行仿真验证,将输出数据进行FFT处理之后,由分析结果得出设计是否能够满足我们的性能需求。通过编写相应的Verilog语言来对该滤波器进行综合,包括硬件电路设计以及FPGA验证。Σ-△调制器输出有效位数为11.66 bit,经过三级数字抽取滤波器之后有效分辨率达到11.51 bit,验证结果显示本文设计满足我们的需求。
[Abstract]:危-ADC is a very important part of integrated chip. In recent years, 危-ADC has been studied more deeply, and its application is becoming more and more extensive. Digital decimation filter is very important to 危-ADC performance. The optimized filter can effectively reduce the area of the whole design and reduce the power consumption. In this paper, Sigma-Delta ADC, is introduced briefly and the two key techniques of over-sampling and noise shaping to realize high resolution are described. The modulator Simulink model is also implemented. Then the overall structure of the filter is determined after the research and analysis, and the design and optimization of the filter at all levels are completed by using MATLAB according to the corresponding index parameters. In order to achieve the goal of low power consumption and small area, the digital filter designed in this paper selects a more advantageous cascade structure, including CIC filter, FIR compensation filter and half band filter. Because the modulator in this paper is single-stage, the comb filter is designed as a two-stage cascaded recursive structure, which can effectively reduce the area and power consumption. Because of some disadvantages of CIC filter, we must add a FIR compensation filter to compensate it, that is to say, we can compensate for passband attenuation. In order to reduce the computational complexity, the coefficients of FIR compensation filter and half band filter are coded by CSD. In this paper, the modulator and filter are modeled in Simulink and verified by simulation. After the output data are processed by FFT, the analysis results show whether the design can meet our performance requirements. The filter is synthesized by writing the corresponding Verilog language, including hardware circuit design and FPGA verification. The effective bit number of 危-modulator output is 11.66 bit,. After the three-stage digital decimation filter, the effective resolution reaches 11.51 bit,. The results show that the design meets our needs.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713

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