基于90nm工艺带LDO驱动频率可修调的振荡器设计
发布时间：2018-11-29 12:29
【摘要】：随着集成电路的高速发展,对芯片时钟频率精确度的要求也越来越高。频率源的准确性可以决定一个时序电路设计的质量。尤其是在如今高速集成的数字电路中,一个细小的时钟误差就可能导致整体周期的错乱,使得数字电路的时序紊乱。因此,振荡器作为集成电路频率源的代表成为了人们关注的研究课题。本论首先文介绍了目前较为流行的三种在集成电路中应用的振荡器,它们分别是晶体振荡器、环形振荡器以及张弛振荡器。随之逐一地分析了它们的结构特点以及工作方原理。本文基于TSMC90nm工艺设计了一款频率可修调的张弛振荡器,并且还设计了一款低功耗的线性稳压器来驱动振荡器。文中详细地阐述了线性稳压器的设计原理,并结合其自身的特点提出了一种低功耗并且十分节省面积的设计方案。随后对其进行仿真验证,得到了一个可靠的输出电压为1.2V的线性稳压器。仿真结果表明线性稳压器的负载调整率为3.64%以及其电源抑制比为-63.4dB。随后,根据设计要求完成了对振荡器电路的总体结构设计和子模块的电路设计。并详细地讲述了如何通过修调控制端口的连接方式来得到所需的输出振荡频率。通过调节控制端口课时输出频率覆盖范围达到默认值的284%至61.5%内,并且仿真数据验证了在如此大的范围内一定可以找到最初设定的频率为48MHz的振荡器。而后为了确保输出时钟的可靠性,还专门地讨论了其相位噪声,仿真实验结果测得相位噪声可达-101.128dBc/Hz @1MHz,以及-121.806dBc/Hz @10MHz。最后,本文绘制出了线性稳压器与振荡器的版图,并分别对其进行后仿验证,仿真结果均满足设计要求。
[Abstract]:With the rapid development of integrated circuits, the precision of clock frequency is becoming more and more important. The accuracy of the frequency source can determine the quality of a sequential circuit design. Especially in today's high-speed integrated digital circuits, a small clock error may lead to the disorder of the whole cycle and the timing disorder of the digital circuits. Therefore, oscillator as the representative of integrated circuit frequency source has become a research topic. This paper first introduces three kinds of oscillators used in integrated circuits, which are crystal oscillator, ring oscillator and Zhang Chi oscillator. Then the structural characteristics and the working principle are analyzed one by one. In this paper, a frequency adjustable Zhang Chi oscillator is designed based on TSMC90nm process, and a low power linear voltage regulator is designed to drive the oscillator. In this paper, the design principle of linear voltage regulator is described in detail, and a design scheme of low power consumption and very low area saving is put forward according to its own characteristics. A reliable linear voltage regulator with 1.2 V output voltage is obtained by simulation. The simulation results show that the load adjustment rate of the linear regulator is 3.64% and the power rejection ratio is -63.4 dB. Then, the overall structure of the oscillator circuit and the circuit design of the sub-module are completed according to the design requirements. How to obtain the output oscillation frequency by adjusting the connection mode of the control port is described in detail. By adjusting the output frequency coverage range of the control port within 284% to 61.5% of the default value, the simulation data verify that the oscillator with the initial frequency of 48MHz can be found in such a wide range. Then, in order to ensure the reliability of the output clock, the phase noise of the clock is also discussed. The simulation results show that the phase noise can reach-101.128dBc/Hz @ 1MHz, and-121.806dBc/Hz @ 10MHz. Finally, the layout of the linear voltage regulator and the oscillator is drawn, and the simulation results meet the design requirements.
【学位授予单位】：北方工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN752
本文编号：2364998
[Abstract]:With the rapid development of integrated circuits, the precision of clock frequency is becoming more and more important. The accuracy of the frequency source can determine the quality of a sequential circuit design. Especially in today's high-speed integrated digital circuits, a small clock error may lead to the disorder of the whole cycle and the timing disorder of the digital circuits. Therefore, oscillator as the representative of integrated circuit frequency source has become a research topic. This paper first introduces three kinds of oscillators used in integrated circuits, which are crystal oscillator, ring oscillator and Zhang Chi oscillator. Then the structural characteristics and the working principle are analyzed one by one. In this paper, a frequency adjustable Zhang Chi oscillator is designed based on TSMC90nm process, and a low power linear voltage regulator is designed to drive the oscillator. In this paper, the design principle of linear voltage regulator is described in detail, and a design scheme of low power consumption and very low area saving is put forward according to its own characteristics. A reliable linear voltage regulator with 1.2 V output voltage is obtained by simulation. The simulation results show that the load adjustment rate of the linear regulator is 3.64% and the power rejection ratio is -63.4 dB. Then, the overall structure of the oscillator circuit and the circuit design of the sub-module are completed according to the design requirements. How to obtain the output oscillation frequency by adjusting the connection mode of the control port is described in detail. By adjusting the output frequency coverage range of the control port within 284% to 61.5% of the default value, the simulation data verify that the oscillator with the initial frequency of 48MHz can be found in such a wide range. Then, in order to ensure the reliability of the output clock, the phase noise of the clock is also discussed. The simulation results show that the phase noise can reach-101.128dBc/Hz @ 1MHz, and-121.806dBc/Hz @ 10MHz. Finally, the layout of the linear voltage regulator and the oscillator is drawn, and the simulation results meet the design requirements.
【学位授予单位】：北方工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN752
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