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应用于音频设备的14bit∑-ΔADC的研究与设计

发布时间:2018-12-11 17:49
【摘要】:Sigma-delta模数转化器(ADC)采用过采样技术、噪声整形技术和数字滤波技术,完成对模拟信号的高精度转换。本文针对AUDIO CODEC IP核项目的实际需求,设计了一款应用于音频设备的14bitSigma-delta ADC,包括sigma-delta模拟调制器部分和数字滤波器部分。Sigma-delta ADC的调制器部分,采用过采样率(OSR)为256倍的2阶1bit CIFB结构。首先通过行为级综合得到Sigma-delta调制器的噪声传输函数,然后运用包含了电路级噪声和非理想因素影响的simulink模型进行行为级仿真,最终电路实现。Sigma-delta ADC的数字滤波器部分,采用三级有限脉冲响应(FIR)抽取滤波器级联结构,顺次为梳状滤波器(CIC)/半袋滤波器(HBF1)/半带滤波器(HBF2)。通过行为级simulink建模仿真并最终交付数字前端完成Verilog HDL编写。在华力55nm CMOS工艺下,Sigma-delta调制器部分采用的是开关电容积分电路来实现的。在调制器电路设计上,各级积分器采用特殊的开关控制以减小电容面积;设计了两级运算放大器、两相不交叠时钟、动态锁存比较器;带隙基准源电路为带高阶补偿的拓扑结构,温度系数(TC)可达到4.87ppm/℃。对整个调制器部分完成了测试,其结果可以达到SNDR=84.1dB(13.67 bits),满足设计需求。
[Abstract]:Sigma-delta analog-to-digital converter (ADC) uses over-sampling technology, noise shaping technology and digital filtering technology to complete the high-precision conversion of analog signals. According to the actual requirement of AUDIO CODEC IP nuclear project, this paper designs a 14bitSigma-delta ADC, for audio equipment, which includes sigma-delta analog modulator part and digital filter part. Sigma-delta ADC modulator part. The second order 1bit CIFB structure with an oversampling rate of 256-fold (OSR) is adopted. First, the noise transfer function of Sigma-delta modulator is obtained by synthesizing the behavior level, then the behavioral level simulation is carried out by using the simulink model which includes the circuit level noise and the influence of non-ideal factors. Finally, the digital filter part of Sigma-delta ADC is realized by the circuit. A cascade structure of three-stage finite pulse response (FIR) decimation filter is adopted. The sequence is comb filter (CIC) / half-bag filter (HBF1) / half-band filter (HBF2). Through behavioral simulink modeling and simulation and finally delivered to the digital front-end to complete the Verilog HDL programming. In the 55nm CMOS process, the Sigma-delta modulator is implemented by the switched capacitor integral circuit. In the circuit design of modulator, the integrator adopts special switch control to reduce the capacitance area, a two-stage operational amplifier, two phase non-overlapping clock, dynamic latch comparator is designed. The bandgap reference circuit is a topology with high order compensation, and the temperature coefficient (TC) can reach 4.87ppm/ 鈩,

本文编号:2372968

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