JPEG2000位平面解码器VLSI结构设计

发布时间：2018-12-13 23:09

【摘要】：随着计算机技术、通信技术、网络技术等技术快速发展,数字图像被广泛应用于通信、互联网、医疗、电子商务、遥感卫星、军事、法律等各个领域,导致数据量呈指数级增长。巨大的数据量对图像的处理、存储和传输造成极大压力,因此图像压缩技术在数字图像应用中具有重要作用。JPEG2000是一种性能优越的图像压缩标准,具有码率可控、压缩倍数高、适合网络传输等优点,对自然图像、合成图像、卫星图像、医学图像等各类图像均具有良好的适用性。目前国内已有西安电子科技大学图像传输与处理研究所研制的高性能JPEG2000编码芯片“雅芯二号”用于航天领域,但是JPEG2000解码系统的高速硬件实现仍有待突破。其主要原因是复杂的解码算法使JPEG2000难以满足实时性处理要求,尤其是JPEG2000中的位平面解码部分的算法复杂度高、开发周期长、处理时延大,造成JPEG2000高速硬件解码系统实现困难。因此,深入研究JPEG2000位平面解码器硬件实现具有重要意义。在结合JPEG2000算法标准和FPGA硬件平台特点的基础上,本研究的总体目标是在Xilinx公司的VC707开发板上实现JPEG2000解码系统,达到入口速率是100Mbps。本文研究的主要内容有以下两部分:(1)本文设计了采取列扫描、列跳过方案的3×4的寄存器扫描窗口,并对一列样本点的上下文采取预计算的方法,给出了寄存器窗口、上下文生成及更新、四种编码原语的VLSI结构,同时给出了三个通道的状态跳转图,并采用高级综合HLS(High-level Synthesis)实现位平面解码部分。对比传统手写代码的开发方式,HLS具有开发速度快、方案调整灵活的优点,因而整个位平面解码器采用HLS实现。(2)本文深入分析JPEG2000解码系统各部分处理速度,制定了高效存储调度方案并完成DDR(Double Data Rate SDRAM)控制器的设计。本文的工作重点是JPEG2000解码系统中位平面解码部分以及DDR存储调度部分的研究和实现。采用HLS完成了位平面解码器设计,解决了传统手写Verilog/VHDL代码开发周期长、开发流程复杂的问题,并且能通过HLS约束形成各种结构适用于不同速度、不同资源需求的应用场景。在VC707开发板上实现后,位平面解码器出口速率最高达98.1Mbps,资源占用在3%以内,比标准算法串行解码的结构平均吞吐率提高5倍,资源占用减少一半以上。结合高效的DDR存储调度方案,可对入口速率为100Mbps、压缩倍数为2倍和4倍的码流进行处理,能满足一般的实时处理要求。
[Abstract]:With the rapid development of computer technology, communication technology and network technology, digital image is widely used in many fields, such as communication, Internet, medical treatment, electronic commerce, remote sensing satellite, military, law, etc. This results in an exponential increase in the amount of data. Huge amount of data exerts great pressure on image processing, storage and transmission, so image compression technology plays an important role in digital image application. JPEG2000 is an excellent image compression standard with controllable code rate and high compression multiple. It is suitable for network transmission and has good applicability to natural image, synthetic image, satellite image, medical image and so on. At present, the high performance JPEG2000 coding chip "Yaxin 2" developed by the Institute of Image Transmission and processing of Xi'an University of Electronic Science and Technology has been used in the aerospace field in China, but the high-speed hardware implementation of the JPEG2000 decoding system still needs to be broken through. The main reason is that the complex decoding algorithm makes it difficult for JPEG2000 to meet the requirements of real-time processing. Especially, the bitplane decoding part of JPEG2000 has high complexity, long development cycle and long processing delay, which makes it difficult to implement JPEG2000 high-speed hardware decoding system. Therefore, it is of great significance to study the hardware implementation of JPEG2000 bit plane decoder. Based on the JPEG2000 algorithm standard and the characteristics of FPGA hardware platform, the overall goal of this study is to implement the JPEG2000 decoding system on the VC707 development board of Xilinx Company, and the entry rate is 100 Mbps. The main contents of this paper are as follows: (1) this paper designs a 3 脳 4 register scanning window with column scan and column skipping scheme, and gives a register window by using predictive calculation method for the context of a list of sample points. Context generation and update, VLSI structure of four encoding primitives, and the state jump diagram of three channels are given, and the bit plane decoding part is implemented by advanced synthetic HLS (High-level Synthesis). Compared with the traditional handwritten code development, HLS has the advantages of fast development speed and flexible scheme adjustment, so the whole bit-plane decoder is implemented by HLS. (2) the processing speed of each part of JPEG2000 decoding system is deeply analyzed in this paper. An efficient storage scheduling scheme is developed and the design of DDR (Double Data Rate SDRAM) controller is completed. This paper focuses on the research and implementation of the median bit plane decoding part and the DDR storage scheduling part of the JPEG2000 decoding system. The bit plane decoder is designed by using HLS, which solves the problems of long development cycle and complex development process of traditional handwritten Verilog/VHDL code, and can form various kinds of application scenarios with different speed and different resource requirements through HLS constraints. When implemented on the VC707 development board, the output rate of the bit-plane decoder is up to 98.1Mbpss, and the resource consumption is less than 3%, which is five times higher than the average throughput of the standard serial decoding structure, and the resource consumption is reduced by more than half. Combined with the efficient DDR storage scheduling scheme, the code stream with 100Mbpss entry rate, 2 times compression times and 4 times compression ratio can be processed, which can meet the general real-time processing requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN764

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