基于VHDL的数字SoC设计与验证的全面自动化实现

发布时间：2018-12-16 16:00

【摘要】：遵循着摩尔定律的指导,半导体行业发展日新月异。IP复用技术使得片上集成功能迅速增多,以SoC为代表的片上结构复杂度不断增加,给数字IC前端的设计和验证上带来巨大挑战。为了保证上市时间,产品开发周期越来越短,多项目同时进行或流水进行已经司空见惯,设计工程师和验证工程师面临着巨大的压力和考验。为了提高设计和验证工作的效率和质量,自动化生成是必须要采取的可行性手段。因此本文提出采用可复用的自动化脚本和工具作为解决方案。本论文基于本人实习所在公司的项目,以SoC上的系统控制单元为例,对其功能进行了简单的介绍,着重介绍了系统控制单元的核心功能——复位管理。对于设计工作,由于复位管理具有很强的规律性,满足自动化生成的条件。因此可以利用脚本生成通用的复位模型。另外还介绍了如何使用脚本工具生成子模块互联所产生的层次以及生成寄存器模块。对于验证工作,测试平台是任何模块或IP进行功能仿真所必须搭建的,为了节约验证工程师搭建测试平台的时间,我们采用脚本对其进行自动化生成。测试用例是验证目标的具体实现形式,包含输入激励和输出校验。复位模块接受多种复位源并且输出一百余个复位信号,要覆盖所有情景时测试用例的编写非常繁杂,因此我们同样采用脚本对其进行自动化生成。最后为了验证自动化代码的正确性,本文采用了依赖测试平台和测试用例的功能仿真,以及不依赖激励的形式验证,以差异化的手段确保代码功能符合需求。目前,本文所采用的自动化生成技术已经十分成熟和稳定。工程师只需要对Perl脚本做很小的调整,便可复用于多个不同的项目。
[Abstract]:Guided by Moore's Law, the semiconductor industry is developing with each passing day. IP reuse technology makes the on-chip integration function increase rapidly, and the complexity of on-chip structure, represented by SoC, increases continuously. It brings great challenges to the design and verification of digital IC front end. In order to ensure the time to market, the product development cycle is getting shorter and shorter. It is common for many projects to be carried out at the same time or running in water. Design engineers and verification engineers are faced with great pressure and test. In order to improve the efficiency and quality of design and verification, automatic generation is a feasible means to be adopted. Therefore, this paper proposes to use reusable automated scripts and tools as a solution. Based on the project of my internship company, this paper introduces the function of the system control unit on SoC, and introduces the core function of the system control unit-reset management. For the design work, because of the strong regularity of reset management, the condition of automatic generation is satisfied. Therefore, a generic reset model can be generated using scripts. In addition, it also introduces how to use script tools to generate the hierarchy of sub-modules and generate register modules. For the verification work, the test platform must be built for any module or IP to simulate the function. In order to save the time for the verification engineer to build the test platform, we use scripts to automate the generation of the test platform. Test cases are specific forms of implementation of validation goals, including input incentives and output validation. The reset module accepts multiple reset sources and outputs more than 100 reset signals. To cover all scenarios the writing of test cases is very complicated so we also use scripts to automatically generate them. Finally, in order to verify the correctness of the automation code, this paper uses functional simulation based on test platform and test cases, and does not rely on incentive to ensure that the code functions meet the requirements by the means of differentiation. At present, the automatic generation technology used in this paper has been very mature and stable. Engineers can reuse Perl scripts across multiple projects with minimal tweaks.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402

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