高动态低信噪比环境下解调器的设计与实现

发布时间：2018-12-17 11:29

【摘要】：随着卫星技术的飞速发展，空间飞行器的数量迅速增加，卫星通信的需求越来越大。受天线增益、平台规模的限制以及收发信机的相对运动，通信双方常在高动态低信噪比环境下进行通信。在高动态低信噪比环境下，传统解调器无法完成同步任务解调数据，，研究高动态低信噪比环境下解调器的设计对通信双方实现通信至关重要。根据高动态低信噪比的特定环境，本文提出了粗同步加精同步的两级载波同步方案。粗同步采用两级调频率逼近算法估计信号参数，估计出的频偏及频率变化率进行初值抵消获得动态变小的信号。采用扩展卡尔曼滤波算法实时估计信号相偏进行精同步。符号同步算法中，通过对比模N积分算法和法罗内插算法，采用性能优越、实现简单的模N积分算法。本文在对各种同步算法仿真研究的基础上综合评估各种算法性能及实现复杂度，选择合适算法构建解调器系统，对解调器整体性能进行Matlab仿真，仿真结果证明本文设计的解调器在高动态低信噪比环境下能同步解调数据，误码率相比BPSK理论值有约0.5dB的性能损失。本文还实现了基于VHDL语言的解调器逻辑实现，并在硬件平台上完成调试工作，硬件测试结果表明在硬件平台上解调器误码率相比BPSK理论值有约1dB的性能损失。
[Abstract]:With the rapid development of satellite technology, the number of space vehicles is increasing rapidly, and the demand for satellite communication is increasing. Due to the antenna gain, the limitation of platform size and the relative motion of transceiver, both sides often communicate in high dynamic and low SNR environment. In the environment of high dynamic and low signal-to-noise ratio, the traditional demodulator can not complete the synchronous task demodulation data, so it is very important to study the design of demodulator in the environment of high dynamic and low signal-to-noise ratio. According to the special environment of high dynamic and low signal-to-noise ratio, a two-stage carrier synchronization scheme for coarse synchronization and refined synchronization is proposed in this paper. In rough synchronization, two-stage frequency modulation approximation algorithm is used to estimate the signal parameters, and the estimated frequency offset and frequency change rate are used to cancel the initial value to obtain the signal with dynamic reduction. The extended Kalman filter (EKF) algorithm is used to estimate the signal phase offset in real time for precise synchronization. In the symbol synchronization algorithm, a simple modular N integral algorithm is implemented by comparing the modular N integral algorithm with the Farrow interpolation algorithm. Based on the simulation of various synchronization algorithms, this paper comprehensively evaluates the performance and implementation complexity of various algorithms, selects the appropriate algorithm to construct the demodulator system, and simulates the overall performance of the demodulator by Matlab. The simulation results show that the demodulator designed in this paper can synchronize the demodulation data in high dynamic and low SNR environment, and the bit error rate (BER) is about the loss of 0.5dB compared with the theoretical value of BPSK. This paper also implements the logic implementation of demodulator based on VHDL language, and accomplishes the debugging work on hardware platform. The hardware test results show that the demodulator bit error rate on the hardware platform is about the loss of 1dB compared with the theoretical value of BPSK.
【学位授予单位】：北京理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN763

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