应用于高速电路中的电荷泵锁相环设计
发布时间：2018-12-17 17:12
【摘要】：锁相环是高速串行接口电路和无线通信系统中时钟发生器的核心模块。随着信息流量不断增长,系统复杂度日益提高,系统对锁相环的工作速率、面积、功耗以及抖动性能的要求也越来越高。本论文设计了用于高速串行接口电路中的电荷泵锁相环。首先对电荷泵锁相环进行了系统分析,包括系统的线性模型、噪声模型以及稳定性。借助于MATLAB系统仿真软件,确定了系统的环路参数。对比实际设计的晶体管级电路仿真结果和MATLAB系统模型的仿真结果,发现结果基本一致。电路设计中,由于输入参考频率较低,鉴频鉴相器采用了经典的基于锁存器的结构,通过调节反馈回路的延时,满足消除鉴相死区的情况下,尽可能地减小了盲区,提高了鉴相精度；电荷泵采用带运算放大器箝位的单端结构,其中尾电流源采用高摆幅的共源共栅结构,在得到高输出阻抗的同时保证了较高的输出摆幅,开关管采用互补开关以抑制电荷注入效应；环路滤波器使用2阶无源滤波器；压控振荡器使用三级差分环形结构,并加入了正反馈交叉耦合对,使输出波形电平转换速度更快、对称性更好,达到降低相位噪声的效果；由于分频比较高,分频器使用脉冲吞咽结构,其中预分频器采用基于TSPCD触发器的结构。论文完成了电路设计、前仿真、版图设计及后仿真。本设计基于SMIC 0.13μm CMOS工艺,由后仿真结果看出,TT工艺角下,当输入参考时钟频率为2MHz, VCO输出信号频率为800MHz时,锁相环总功耗为5.4mA×3.3V,锁定时间小于40μs,VCO输出相位噪声为-102dBc/Hz@1MHz,系统环路输出峰峰抖动最大值24.9ps@800MHz,版图核心面积为0.315mm×0.285mm。
[Abstract]:PLL is the core module of clock generator in high speed serial interface circuit and wireless communication system. With the increasing of the information flow and the increasing complexity of the system, the requirements of the system for the speed, area, power consumption and jitter performance of the PLL are becoming higher and higher. In this paper, a charge pump phase locked loop (CPPLL) is designed for high speed serial interface circuit. Firstly, the charge pump phase-locked loop is analyzed systematically, including the linear model, noise model and stability of the system. With the help of MATLAB system simulation software, the loop parameters of the system are determined. Compared with the simulation results of the transistor level circuit designed in practice and the MATLAB system model, it is found that the results are basically the same. In the design of the circuit, because of the low input reference frequency, the phase discriminator adopts the classical structure based on latch. By adjusting the delay of the feedback loop, the blind area is reduced as much as possible under the condition of eliminating the dead zone of phase detection. The precision of phase detection is improved. The charge pump uses a single-terminal structure clamped with an operational amplifier, in which the tail current source adopts a high swing common-gate structure, which can obtain a high output impedance and ensure a higher output swing. The switching tube adopts complementary switch to suppress charge injection effect. The loop filter uses a second-order passive filter, the voltage-controlled oscillator uses a three-stage differential ring structure, and a positive feedback cross-coupling pair is added, which makes the output waveform level conversion faster and the symmetry better, thus reducing the phase noise. Because of the high frequency division, the frequency divider uses pulse swallowing structure, in which the predivider adopts the structure based on TSPCD flip-flop. Circuit design, pre-simulation, layout design and post-simulation are completed in this paper. The design is based on SMIC 0.13 渭 m CMOS process. The post-simulation results show that when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz, the total power consumption of the PLL is 5.4mA 脳 3.3 V, and the locking time is less than 40 渭 s, when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz. The phase noise of VCO output is -102dBc / Hz @ 1MHz, and the maximum output peak jitter of system loop is 24.9ps @ 800MHz. The core area of VCO is 0.315mm 脳 0.285mm.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402
本文编号：2384539
[Abstract]:PLL is the core module of clock generator in high speed serial interface circuit and wireless communication system. With the increasing of the information flow and the increasing complexity of the system, the requirements of the system for the speed, area, power consumption and jitter performance of the PLL are becoming higher and higher. In this paper, a charge pump phase locked loop (CPPLL) is designed for high speed serial interface circuit. Firstly, the charge pump phase-locked loop is analyzed systematically, including the linear model, noise model and stability of the system. With the help of MATLAB system simulation software, the loop parameters of the system are determined. Compared with the simulation results of the transistor level circuit designed in practice and the MATLAB system model, it is found that the results are basically the same. In the design of the circuit, because of the low input reference frequency, the phase discriminator adopts the classical structure based on latch. By adjusting the delay of the feedback loop, the blind area is reduced as much as possible under the condition of eliminating the dead zone of phase detection. The precision of phase detection is improved. The charge pump uses a single-terminal structure clamped with an operational amplifier, in which the tail current source adopts a high swing common-gate structure, which can obtain a high output impedance and ensure a higher output swing. The switching tube adopts complementary switch to suppress charge injection effect. The loop filter uses a second-order passive filter, the voltage-controlled oscillator uses a three-stage differential ring structure, and a positive feedback cross-coupling pair is added, which makes the output waveform level conversion faster and the symmetry better, thus reducing the phase noise. Because of the high frequency division, the frequency divider uses pulse swallowing structure, in which the predivider adopts the structure based on TSPCD flip-flop. Circuit design, pre-simulation, layout design and post-simulation are completed in this paper. The design is based on SMIC 0.13 渭 m CMOS process. The post-simulation results show that when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz, the total power consumption of the PLL is 5.4mA 脳 3.3 V, and the locking time is less than 40 渭 s, when the input reference clock frequency is 2 MHz and the VCO output signal frequency is 800MHz. The phase noise of VCO output is -102dBc / Hz @ 1MHz, and the maximum output peak jitter of system loop is 24.9ps @ 800MHz. The core area of VCO is 0.315mm 脳 0.285mm.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402
【参考文献】
相关期刊论文 前1条
1 ;Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL[J];The Journal of China Universities of Posts and Telecommunications;2011年06期
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