650V功率VDMOS结终端扩展优化设计
发布时间：2018-12-25 11:07
【摘要】：高压VDMOS器件需要借助终端结构来缓解结弯曲引起的曲率效应。在VDMOS器件设计中,高击穿电压、短终端长度、低漏电流和低表面电场峰值等性能参数的终端结构对芯片的稳定性和可靠性至关重要。联合传统的场板、场限环、结终端扩展(JTE)等终端技术形成的复合终端结构在学术界获得广泛研究。本文对650V VDMOS器件的多场限环(MFLR)、复合场板多场限环(FP-MFLR)、单区JTE和复合场板JTE(FP-JTE)四种终端结构进行优化设计。通过分析PN结耐压机理,采用碰撞电离率Lackner模型对650V VDMOS元胞结构进行仿真设计。并对其静态参数进行测试,击穿电压达到773.3V,导通电阻为6.73Ω,阈值电压为2.66V,满足了设计要求。此结构为穿通型设计,最大电场为2.55×10~5V/cm。在确定元胞结构外延参数的基础上,不改变工艺条件对单场限环、多场限环、金属与多晶硅复合场板及单区JTE结构进行优化。研究发现,主结与场限环同时击穿时,击穿点并不在同一水平线上,而是由内向外逐渐靠近硅表面;最外环为非穿通型击穿,其余各环为穿通型击穿,各环结表面电场峰值从主结处由内向外逐渐增大,主结处表面电场峰值略低于场限环处;金属场板完全笼盖住多晶硅,适当的多晶硅和金属场板长度使表面电场呈现三个峰值,多晶硅场板拉低主结与金属场板两处的表面电场峰值;密封保护环或者沟道截止环放置在耗尽层边界外以避免对终端结构的耐压造成影响。基于此,设计的6FLRs终端结构耐压达到679V,在183.8μm的终端长度下,将表面电场峰值降低至2.34×10~5V/cm;将FP-MFLR结构的终端长度缩小至171.8μm,其耐压达到700.0V,表面电场低至2.11×10~5V/cm;单区JTE结构的耐压为713.4V,终端长度进一步缩小至141.8μm,表面电场峰值在四种结构中最小,值为1.9×10~5V/cm;FP-JTE结构的击穿电压达到最大,值为757.7V,耐压效率98%,几乎接近元胞区结构的击穿电压,具有最小的终端长度139.2μm,表面电场峰值为2.28×1 05V/cm。除此之外,四种终端结构均相容于传统工艺,操作方便易实现。同时,FP-MFLR与FP-JTE结构受界面电荷影响小,稳定性和可靠性相对较高。
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386
本文编号：2391074
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386
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