一种高效片间互联接口协议的设计与实现

发布时间：2019-01-05 19:22

【摘要】：随着半导体工艺的日趋成熟,超大规模集成电路迅猛发展。但传统的单核处理器性能,与当前亟待研究的计算密集型应用需求,如核能开发、宇宙空间探索,以及炙手可热的人工智能,仍存在不可逾越的鸿沟。因此,计算机体系结构逐渐由单核向多核、众核、多片发展。以Intel为代表的同构多核、多片系统与以NVIDIA为代表的异构多核、多片系统,逐渐成为芯片设计的必然趋势。在此背景下,如何准确、高效地传输数据,成为多核、多片系统中至关重要的技术重心与设计难点。片间互联接口协议主要有两种:支持路由功能的胖树结构协议,与不支持路由功能的全互联结构协议。当计算处理器核数小于8时,由于胖树结构协议控制模块设计复杂,多核之间需要交换机进行数据转发,所以互联结构占用的面积与功耗较大。片间互联的实现技术主要包含两种:串行技术和并行技术。但随着芯片面积逐渐减小,并行互联技术中,互联线间实现物理绝缘难度加大,时钟偏差与信号串扰也日趋严重,此外,该技术需要占用芯片大量的引脚数,增大了封装难度与成本,降低了可靠性。因此,一种高效、可靠的全互联串行互联接口协议对于多片架构设计具有十分重要的意义。针对应用领域对片间互联接口实时性和高带宽的需求,本文深入调研现有的互联协议,提出一种基于“包”,具备低延迟、高带宽以及高扩展性的全互联串行互联接口协议SLink。该协议由事务层、数据链路层和物理层三个部分组成。协议“包”格式简洁,选择LVDS技术作为物理层的数据传输基础,支持可配置的CRC校验和硬件检测重传机制。基于SLink协议定义,提出一种实现方案,给出仿真评估数据及FPGA的验证结果。实验结果说明,相比PCI-Express 2.0接口,SLink接口传输延时平均减少61.0%,有效带宽平均增加55.6%,控制器所占面积减小约97.5%。
[Abstract]:With the development of semiconductor technology, VLSI is developing rapidly. However, there is still an insurmountable gap between the performance of traditional single-core processors and the needs of computational intensive applications, such as nuclear energy development, space exploration, and the hot artificial intelligence. Therefore, the computer architecture is gradually developing from single core to multi-core, multi-core and multi-chip. Isomorphic multicore, multi-chip system represented by Intel and heterogeneous multi-core and multi-chip system represented by NVIDIA are becoming the inevitable trend of chip design. Under this background, how to transmit data accurately and efficiently becomes the most important technical center of gravity and design difficulty in multi-core and multi-chip system. There are two kinds of inter-chip interfacing protocols: fat tree protocol which supports routing function and full interconnection protocol which does not support routing function. When the number of processor cores is less than 8, due to the complexity of the design of the protocol control module of the fat-tree structure and the need for the switch to transmit the data between the multi-cores, the area and power consumption of the interconnected architecture are large. The realization technology of interchip interconnection mainly includes two kinds: serial technology and parallel technology. However, as the chip area decreases gradually, in parallel interconnection technology, it is more difficult to realize physical insulation between interconnection lines, clock deviation and signal crosstalk are becoming more and more serious. In addition, this technology needs to occupy a large number of pins on the chip. It increases the difficulty and cost of packaging and reduces the reliability. Therefore, an efficient and reliable protocol of fully interconnected serial interconnect interface is very important to the design of multi-chip architecture. In order to meet the requirement of real-time and high bandwidth of inter-chip interconnection interface in application field, this paper investigates the existing interconnection protocols, and proposes a fully interconnected serial interface protocol SLink. based on packet, with low delay, high bandwidth and high expansibility. The protocol consists of three parts: transaction layer, data link layer and physical layer. The protocol "packet" format is simple, LVDS technology is selected as the physical layer of data transmission basis, support configurable CRC verification and hardware detection retransmission mechanism. Based on the definition of SLink protocol, an implementation scheme is proposed, and the simulation evaluation data and the verification results of FPGA are given. The experimental results show that compared with PCI-Express 2.0 interface, the average transmission delay of SLink interface is reduced by 61.0, the effective bandwidth is increased by 55.6, and the area occupied by the controller is reduced by about 97.5.
【学位授予单位】：哈尔滨理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN405.97

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