基于65nm CMOS的10位低功耗逐次逼近ADC

发布时间：2019-01-06 16:24

【摘要】：随着现代科技的发展,植入式生物医疗设备已成为热点研究方向之一,相比于传统便携式医疗设备更具灵活性,对于疾病的诊治有十分重要的意义。然而,如何使植入式医疗设备更为安全、稳定地造福患者,仍面临巨大的挑战,尤其对于植入式芯片,不仅其外形和尺寸受到解剖部位的限制,芯片工作时的功耗散热也会损伤解剖部位的机体组织。逐次逼近(SAR:Successive-Approximation-Register)模/数转换器(ADC: Analog-to-Digital Converter)具有结构简单、面积小、功耗低等特点,广泛应用于生物医疗电子领域。本文针对植入式生物芯片应用,重点对SAR ADC进行功耗与面积优化,完成电路设计、版图设计及仿真验证。本文设计了一种10-bit低功耗SAR ADC,主要由采样/保持电路、D/A转换网络、比较器以及SAR逻辑控制电路构成。通过研究各模块的不同电路结构、探讨影响电路性能的非理想因素,对传统的电荷再分配型SAR ADC电路进行了改进及优化,设计结果满足了植入式生物芯片的低功耗要求。主要采取的设计方案包括：1.由于电容阵列不消耗静态功耗,电荷再分配结构是低功耗SAR ADC的主要结构,本文在分析目前已有的电容阵列结构及开关时序的基础上,提出了一种基于分段电容阵列的新型D/A转换网络及开关时序,重点改进了分段电容阵列中冗余电容的结构,与目前已有的D/A转换网络相比,有效地降低了功耗与面积。2.本文设计的SAR ADC采用基于上极板采样的差分输入结构,一方面差分输入结构能够很好地抑制共模干扰、提高ADC的性能,另外上极板采样有效减小了输入电容阵列的规模,利于功耗和面积优化。3.在其它模块电路方面,采样/保持部分采用自举式开关对输入模拟信号进行采样,其相对恒定的导通电阻保证了采样电路的线性度；本文设计的SAR ADC比较器采用两级级联的动态结构,有效减小了整个ADC的静态功耗；SAR逻辑控制部分采用由动态单元组成的电路,很大程度上减小了逻辑电路的复杂度,降低了数字电路的功耗和面积。整个10-bit SAR ADC采用65nm CMOS工艺设计实现,利用Cadence和Matlab工具进行设计及仿真验证。在电源电压与基准电压为0.8V,采样速率为50KS/s,输入为1.5KHz差分正弦信号时,整个SAR ADC的信噪失真比(SNDR：Signal-to-Noise-and-Distortion Ratio)为61.42dB,有效位数(ENOB:Effective Number of Bits)为9.91,功耗为423nW,品质因数(FoM:Figure of Merit)为8.7fJ/Conv. step。本文设计的SAR ADC版图面积为136μm×176μm,非常适合植入式生物芯片应用。
[Abstract]:With the development of modern science and technology, implantable biomedical devices have become one of the hot research directions. Compared with the traditional portable medical equipment, it is more flexible and has a very important significance for the diagnosis and treatment of diseases. However, how to make implantable medical devices safer and more stable for the benefit of patients still faces enormous challenges, especially for implanted chips, not only in terms of their shape and size, but also because of their anatomical location. The power dissipation of the chip can also damage the anatomical tissue. Successive approximation (SAR:Successive-Approximation-Register) A / D converter (ADC: Analog-to-Digital Converter) is widely used in biomedical electronics due to its simple structure, small area and low power consumption. This paper focuses on the optimization of power consumption and area of SAR ADC, circuit design, layout design and simulation verification for implanted biochip applications. In this paper, a low power 10-bit SAR ADC, is designed, which consists of a sampling / holding circuit, a D / A conversion network, a comparator and a SAR logic control circuit. By studying the different circuit structure of each module and discussing the non-ideal factors that affect the circuit performance, the traditional charge redistribution SAR ADC circuit is improved and optimized. The design results meet the low power requirement of implanted biochip. The main design projects are as follows: 1. Because capacitance array does not consume static power, charge redistribution structure is the main structure of low power SAR ADC. A novel D / A conversion network based on piecewise capacitor array and its switching timing are proposed. The structure of redundant capacitors in piecewise capacitor array is mainly improved, compared with the existing D / A conversion network. Effectively reduced power consumption and area. 2. The SAR ADC designed in this paper adopts differential input structure based on the sampling of upper pole plate. On the one hand, the differential input structure can suppress common-mode interference and improve the performance of ADC. On the other hand, the sampling of upper pole plate can effectively reduce the size of input capacitor array. Conducive to power consumption and area optimization. 3. In other module circuits, the sampling / holding part uses bootstrap switch to sample the input analog signal, and its relatively constant on-resistance ensures the linearity of the sampling circuit. The SAR ADC comparator designed in this paper adopts a two-stage cascade dynamic structure, which effectively reduces the static power consumption of the whole ADC. The logic control part of SAR uses a circuit composed of dynamic cells, which greatly reduces the complexity of the logic circuit and reduces the power consumption and area of the digital circuit. The whole 10-bit SAR ADC is realized by 65nm CMOS process design, and is designed and verified by Cadence and Matlab tools. When the supply voltage and reference voltage are 0.8V, the sampling rate is 50KS / s and the input is 1.5KHz differential sinusoidal signal, the signal to noise distortion ratio (SNDR:Signal-to-Noise-and-Distortion Ratio) of the whole SAR ADC is 61.42 dB. The number of significant bits (ENOB:Effective Number of Bits) is 9.91, power consumption is 423nW, FoM:Figure of Merit) is 8.7 fJ / Conv. Step. The SAR ADC area designed in this paper is 136 渭 m 脳 176 渭 m, which is very suitable for biochip implantation.
【学位授予单位】：西安邮电大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792

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