基于FPGA的USB3.0扰码及解扰码电路研究与设计

发布时间：2019-01-17 12:43

【摘要】：USB3. 0是一种由Intel和Microsoft公司发起创立的接口规范,它以USB2. 0作为基础实现了接口技术的进一步发展。USB2.0的最大传输带宽为480Mbps,而USB3. 0将带宽提高到了 5Gbps,它比USB2. 0更适合传输海量数据文件。USB3. 0比USB2. 0的传输效率高、功耗更低,特别地加强了电源管理功能,并且USB3.0向下兼容USB2.0,方便USB2.0接口产品的升级。USB3.0接口在未来一定会被普遍地应用于电子产品中。本文主要是按照USB3. 0协议的要求设计USB3. 0物理层中的扰码及解扰码电路。USB3.0物理层可分为数字电路模块与模拟电路模块,其中数字电路模块主要由扰码及解扰码电路,8b/1Ob编解码电路,K28. 5检测模块,弹性缓冲器模块,串并及并串转换电路等模块构成。扰码及解扰码电路是USB3. 0物理层数据处理流程中的重要部分,且它与物理层中的8b/10b编解码电路模块相互联系。因此,本文对8b/10b编解码模块也进行研究与设计。论文在分析了 USB3. 0协议中扰码及解扰码的原理与规则后,提出以8位并行方法来实现USB3. 0物理层中的扰码与解扰码电路。本文使用FPGA验证电路逻辑功能,运用Verilog硬件语言描述扰码及解扰码电路,再通过Modelsim仿真软件进行功能上的仿真。结果表明所设计出来的扰码及解码电路满足USB3. 0数据通信协议要求。
[Abstract]:USB3. 0 is an interface specification initiated by Intel and Microsoft, which is based on USB2. The maximum transmission bandwidth of USB2.0 is 480 Mbpss, while that of USB3. is 480 Mbpss. 0 increases the bandwidth to 5 GB pss, which is higher than USB2. 0 is more suitable for transferring massive data files. USB3. 0 ratio USB2. 0 has high transmission efficiency and low power consumption, especially enhanced power management, and USB3.0 is compatible with USB2.0, downwards to facilitate the upgrade of USB2.0 interface products. USB3.0 interface will be widely used in electronic products in the future. This article is mainly based on the USB3. Design USB3. for 0. 0 protocol The physical layer of USB3.0 can be divided into digital circuit module and analog circuit module, in which the digital circuit module mainly consists of scrambling code and descrambling circuit, 8b/1Ob encoding and decoding circuit, K28. Detection module, elastic buffer module, series-parallel and parallel conversion circuit and other modules. Scrambling and unscrambling circuit is USB3. 0 is an important part of the physical layer data processing flow, and it is related to the 8b/10b codec circuit module in the physical layer. Therefore, this paper also carries on the research and the design to the 8b/10b codec module. The paper analyzes the USB3. After the principle and rule of scrambling code and unscrambling code in 0 protocol, an 8-bit parallel method is proposed to implement USB3.. The scrambling code and descrambling circuit in the physical layer. In this paper, the logic function of the circuit is verified by FPGA, and the scrambling code and unscrambling circuit are described by Verilog hardware language, and the functional simulation is carried out by Modelsim simulation software. The results show that the scrambling code and decoding circuit can satisfy USB3.. Data communication protocol requirements.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791;TP334.7

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