电力线载波芯片数字后端设计
发布时间：2019-02-13 08:26
【摘要】：电力线作为一种现代社会基础设施,分布范围极广。智能电表以电力线作为载波介质,受到国内外高度重视。电力线载波(Power Line Carrier,PLC)芯片是智能电表的核心部件。本文对一种具有可扩展射频收发功能的新型电力线载波芯片BES3803进行了研究,主要工作如下:1.基于SMIC 0.18μm mixed signal工艺,使用Design Compiler工具对芯片进行了带有可测试性设计的逻辑综合,将电力线载波芯片用门级电路实现,同时将电路中的时序器件替换为具有可测试性端口的器件,并针对储存器插入自建内测试电路,以供流片后测试用。使用Prime Time工具对逻辑综合生成的门级网表进行了时序分析,再用Formality工具对RTL级代码和生成的门级网表进行形式验证,保证了逻辑综合的正确性。2.基于SMIC 0.18μm mixed signal工艺,使用Astro工具实现了芯片物理版图设计。包括:布局规划、时钟树综合、布线、寄生参数提取、时序分析、物理验证和形式验证。在布局规划中,采用一种模块限定布局、电源网络线宽优化相结合的非均匀阶梯型电源网络优化方法对数字模块电源网络进行改善,释放了芯片绕线空间,减小了芯片面积,优化了芯片功耗。在时钟树综合中,采用一种忽略门控时钟偏移检查的新型时钟树综合、局部时钟树构建的方法进行优化,大幅度减少了时钟缓冲器插入数目,再次优化了芯片功耗,减小了芯片面积。3.对芯片功能、功耗和电压降进行了仿真验证。结果表明,电力线载波芯片功能正确。针对芯片扩展功能,进行了匹配设计。本文设计的电力线载波芯片BES3803完成了芯片从RTL(register-transfer level)到GDSII(graphic design system II)的所有设计工作,最终芯片面积5.87mm2,功耗61.116mW,测试覆盖率98.21%。仿真验证表明,芯片功能正常,且相比原有芯片性能大幅度提高,功能更加强大,具有更强的市场竞争力。
[Abstract]:As a modern social infrastructure, power line is widely distributed. The intelligent ammeter takes the power line as the carrier medium, which is highly valued at home and abroad. Power line carrier (Power Line Carrier,PLC (PLC) chip is the core component of intelligent ammeter. In this paper, a new power line carrier chip BES3803 with extensible RF transceiver is studied. The main work is as follows: 1. Based on the SMIC 0.18 渭 m mixed signal technology, the logic synthesis of the chip with testability design is carried out by using the Design Compiler tool, and the power line carrier chip is realized by the gate circuit. At the same time, the sequential device in the circuit is replaced by the device with testability port, and the self-built test circuit is inserted for the memory to be used for the post-test of the chip. The sequential analysis of gate network table generated by logic synthesis is carried out by using Prime Time tool, and the formal verification of RTL level code and gate network table generated by Formality tool is carried out, which ensures the correctness of logic synthesis. 2. Based on SMIC 0.18 渭 m mixed signal process, the chip physical layout design is realized by using Astro tool. Including: layout planning, clock tree synthesis, routing, parasitic parameter extraction, timing analysis, physical verification and formal verification. In the layout planning, a non-uniform ladder power network optimization method is used to improve the digital module power network, which is designed to limit the layout and optimize the line width of the power supply network, thus freeing the chip winding space and reducing the chip area. The chip power consumption is optimized. In the clock tree synthesis, a new clock tree synthesis method, which ignores the gated clock offset check, is used to optimize the local clock tree construction, which greatly reduces the number of clock buffer inserts and optimizes the chip power consumption. Reduced chip area. 3. The function, power consumption and voltage drop of the chip are simulated and verified. The results show that the power line carrier chip functions correctly. According to the extended function of the chip, the matching design is carried out. The power line carrier chip BES3803 designed in this paper has completed all the design work from RTL (register-transfer level) to GDSII (graphic design system II). Finally, the chip area is 5.87mm-2, the power consumption is 61.116mW, and the test coverage is 98.21mW. The simulation results show that the chip has normal function, and compared with the original chip, the performance of the chip is greatly improved, the function is more powerful, and the chip has stronger market competitiveness.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
本文编号：2421361
[Abstract]:As a modern social infrastructure, power line is widely distributed. The intelligent ammeter takes the power line as the carrier medium, which is highly valued at home and abroad. Power line carrier (Power Line Carrier,PLC (PLC) chip is the core component of intelligent ammeter. In this paper, a new power line carrier chip BES3803 with extensible RF transceiver is studied. The main work is as follows: 1. Based on the SMIC 0.18 渭 m mixed signal technology, the logic synthesis of the chip with testability design is carried out by using the Design Compiler tool, and the power line carrier chip is realized by the gate circuit. At the same time, the sequential device in the circuit is replaced by the device with testability port, and the self-built test circuit is inserted for the memory to be used for the post-test of the chip. The sequential analysis of gate network table generated by logic synthesis is carried out by using Prime Time tool, and the formal verification of RTL level code and gate network table generated by Formality tool is carried out, which ensures the correctness of logic synthesis. 2. Based on SMIC 0.18 渭 m mixed signal process, the chip physical layout design is realized by using Astro tool. Including: layout planning, clock tree synthesis, routing, parasitic parameter extraction, timing analysis, physical verification and formal verification. In the layout planning, a non-uniform ladder power network optimization method is used to improve the digital module power network, which is designed to limit the layout and optimize the line width of the power supply network, thus freeing the chip winding space and reducing the chip area. The chip power consumption is optimized. In the clock tree synthesis, a new clock tree synthesis method, which ignores the gated clock offset check, is used to optimize the local clock tree construction, which greatly reduces the number of clock buffer inserts and optimizes the chip power consumption. Reduced chip area. 3. The function, power consumption and voltage drop of the chip are simulated and verified. The results show that the power line carrier chip functions correctly. According to the extended function of the chip, the matching design is carried out. The power line carrier chip BES3803 designed in this paper has completed all the design work from RTL (register-transfer level) to GDSII (graphic design system II). Finally, the chip area is 5.87mm-2, the power consumption is 61.116mW, and the test coverage is 98.21mW. The simulation results show that the chip has normal function, and compared with the original chip, the performance of the chip is greatly improved, the function is more powerful, and the chip has stronger market competitiveness.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
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，本文编号：2421361
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