NMOS器件热载流子效应研究
发布时间：2019-03-09 19:03
【摘要】：超大规模集成电路的迅速发展,迫切要求提高整个电路系统及单个器件的性能与可靠性,这是因为集成电路是由元器件组成的,单个器件的性能与质量直接决定系统的可靠性。热载流子效应作为重要的可靠性问题之一,通过纵向与横向的高强度电场能够破坏器件氧化层的质量,降低使用寿命,不仅会导致阈值电压、最大跨导以及饱和漏电流等标志器件可靠性的参数漂移,还会引起栅泄漏电流的增大,严重影响电路系统的稳定性与可靠性,因而,对热载流子效应进行深入的研究具有重要的意义。本论文针对NMOS器件中的热载流子效应以及HCI应力导致的栅泄漏电流SILC的退化进行了深入的探究。先从HCI效应的本质出发,探讨引起NMOSFET失效的HCI物理机制,阐述NMOSFET内部热载流子的产生方式与运动规律,重点介绍了有关HCI效应的重要模型,经典的物理模型包括衬底电流模型和幸运电子模型,指出这两种模型分别从衬底电流及栅电流两个方面来描述热载流子的运动过程;其次给出有关探究NMOSFET热载流子效应的不同测试方法,针对Silvaco仿真软件进行了较为详细的说明,指出该软件对于研究NMOS器件热载流子效应的重要辅助作用。通过对栅氧厚度为4nm的NMOS器件进行一系列实验测试,结合仿真软件的模拟结果,研究器件的沟道长度、沟道宽度、应力条件等对衬底电流及栅电流的影响,由此确定导致器件热载流子效应最为严重的最坏HCI应力条件,并研究了最坏应力条件与结构参数的关系,深入分析了沟道长度对最坏栅压的影响以及导致应力条件转变的物理机制;通过间断应力实验,研究了NMOS器件在热载流子应力下的参数退化,主要有阈值电压正向漂移、最大跨导减小以及饱和漏电流降低等,并研究了HCI应力作用下栅泄漏电流退化的机制,认为造成SILC漂移的重要因素是栅氧化层中陷阱电荷的增加,并通过实验证明了热载流子效应能够引起NMOS器件的SILC随应力时间以指数规律增大,结合衬底电流模型与幸运电子模型,将SILC的漂移与阈值电压、衬底电流峰值的漂移进行对比分析,发现它们拟合成一条直线,这说明热载流子效应确实是导致NMOS器件SILC漂移的重要因素,与此同时也可以用HCI效应过程中产生的栅泄漏电流来表征NMOSFET在HCI应力下造成的损伤以及性能的退化。最后,从理论上指出采用间断应力方式进行测试有可能会产生的实验误差,并设计了不间断应力实验,将测试结果与间断应力进行对比,发现确实存在少量的误差,这说明在间断应力测试的过程中,测试时间内器件性能的恢复是存在的,这也为研究HCI应力下NMOS器件的损伤恢复提供了有效的思路与方法。
[Abstract]:With the rapid development of VLSI, it is urgent to improve the performance and reliability of the whole circuit system and single device. This is because the integrated circuit is composed of components, and the performance and quality of the single device directly determine the reliability of the system. Hot carrier effect, as one of the important reliability problems, can destroy the quality of oxide layer and reduce the service life through longitudinal and transverse high strength electric fields, which will not only lead to threshold voltage. The parameter drift of device reliability, such as maximum transconductance and saturation leakage current, will also cause the increase of gate leakage current, which will seriously affect the stability and reliability of the circuit system. It is of great significance to study the hot carrier effect in depth. The hot carrier effect in NMOS devices and the degradation of gate leakage current (SILC) caused by HCI stress are discussed in this paper. Starting from the essence of HCI effect, this paper discusses the physical mechanism of NMOSFET failure, expounds the mode of generation and movement of hot carriers in NMOSFET, and emphatically introduces the important models of HCI effect. The classical physical models include the substrate current model and the lucky electron model. It is pointed out that the two models describe the hot carrier motion from two aspects: the substrate current and the gate current. Secondly, different testing methods for exploring the hot carrier effect of NMOSFET are given, and the Silvaco simulation software is described in detail. It is pointed out that the software plays an important auxiliary role in studying the hot carrier effect of NMOS devices. The effects of channel length, channel width and stress condition on substrate current and gate current of NMOS devices with gate oxygen thickness of 4nm are studied by means of a series of experimental tests, combined with the simulation results of simulation software, and the effects of channel length, channel width and stress conditions on the substrate current and gate current are studied. The worst HCI stress condition which leads to the most serious hot carrier effect of the device is determined and the relationship between the worst stress condition and the structural parameters is studied. The influence of channel length on the worst gate voltage and the physical mechanism of stress condition transformation are analyzed. Through the discontinuous stress experiment, the parameter degradation of NMOS device under hot carrier stress is studied, such as the forward drift of threshold voltage, the decrease of maximum transconductance and the decrease of saturated leakage current, etc. The degradation mechanism of gate leakage current under HCI stress is studied. It is considered that the important factor causing SILC drift is the increase of trap charge in gate oxide. It is proved by experiments that the hot carrier effect can cause the SILC of NMOS devices to increase exponentially with the stress time. The drift and threshold voltage of SILC are combined with the substrate current model and lucky electron model. By comparing and analyzing the drift of the peak current of the substrate, it is found that they fit into a straight line, which indicates that the hot carrier effect is indeed an important factor leading to the SILC drift of the NMOS device. At the same time, the gate leakage current generated in the process of HCI effect can also be used to characterize the damage caused by NMOSFET under HCI stress and the degradation of its performance. Finally, it is pointed out theoretically that there may be experimental errors caused by discontinuous stress testing, and the uninterrupted stress experiment is designed. Comparing the measured results with the discontinuous stress, it is found that there are a few errors. This shows that the recovery of device performance during the test time exists in the process of discontinuous stress testing, which also provides an effective way to study the damage recovery of NMOS devices under HCI stress.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
本文编号：2437766
[Abstract]:With the rapid development of VLSI, it is urgent to improve the performance and reliability of the whole circuit system and single device. This is because the integrated circuit is composed of components, and the performance and quality of the single device directly determine the reliability of the system. Hot carrier effect, as one of the important reliability problems, can destroy the quality of oxide layer and reduce the service life through longitudinal and transverse high strength electric fields, which will not only lead to threshold voltage. The parameter drift of device reliability, such as maximum transconductance and saturation leakage current, will also cause the increase of gate leakage current, which will seriously affect the stability and reliability of the circuit system. It is of great significance to study the hot carrier effect in depth. The hot carrier effect in NMOS devices and the degradation of gate leakage current (SILC) caused by HCI stress are discussed in this paper. Starting from the essence of HCI effect, this paper discusses the physical mechanism of NMOSFET failure, expounds the mode of generation and movement of hot carriers in NMOSFET, and emphatically introduces the important models of HCI effect. The classical physical models include the substrate current model and the lucky electron model. It is pointed out that the two models describe the hot carrier motion from two aspects: the substrate current and the gate current. Secondly, different testing methods for exploring the hot carrier effect of NMOSFET are given, and the Silvaco simulation software is described in detail. It is pointed out that the software plays an important auxiliary role in studying the hot carrier effect of NMOS devices. The effects of channel length, channel width and stress condition on substrate current and gate current of NMOS devices with gate oxygen thickness of 4nm are studied by means of a series of experimental tests, combined with the simulation results of simulation software, and the effects of channel length, channel width and stress conditions on the substrate current and gate current are studied. The worst HCI stress condition which leads to the most serious hot carrier effect of the device is determined and the relationship between the worst stress condition and the structural parameters is studied. The influence of channel length on the worst gate voltage and the physical mechanism of stress condition transformation are analyzed. Through the discontinuous stress experiment, the parameter degradation of NMOS device under hot carrier stress is studied, such as the forward drift of threshold voltage, the decrease of maximum transconductance and the decrease of saturated leakage current, etc. The degradation mechanism of gate leakage current under HCI stress is studied. It is considered that the important factor causing SILC drift is the increase of trap charge in gate oxide. It is proved by experiments that the hot carrier effect can cause the SILC of NMOS devices to increase exponentially with the stress time. The drift and threshold voltage of SILC are combined with the substrate current model and lucky electron model. By comparing and analyzing the drift of the peak current of the substrate, it is found that they fit into a straight line, which indicates that the hot carrier effect is indeed an important factor leading to the SILC drift of the NMOS device. At the same time, the gate leakage current generated in the process of HCI effect can also be used to characterize the damage caused by NMOSFET under HCI stress and the degradation of its performance. Finally, it is pointed out theoretically that there may be experimental errors caused by discontinuous stress testing, and the uninterrupted stress experiment is designed. Comparing the measured results with the discontinuous stress, it is found that there are a few errors. This shows that the recovery of device performance during the test time exists in the process of discontinuous stress testing, which also provides an effective way to study the damage recovery of NMOS devices under HCI stress.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
【参考文献】
相关期刊论文 前8条
1 朱筠;;利用SILVACO TCAD软件改进集成电路实践教学的研究[J];数字技术与应用;2012年07期
2 马晓华;曹艳荣;郝跃;张月;;Hot carrier injection degradation under dynamic stress[J];Chinese Physics B;2011年03期
3 杨国勇,霍宗亮,王金延,毛凌锋,王子欧,谭长华,许铭真;超薄栅MOS器件热载流子应力下SILC的产生机制(英文)[J];半导体学报;2003年06期
4 张进城,郝跃,刘海波;通过直接栅电流测量研究PMOSFET's热载流子损伤[J];半导体学报;2002年01期
5 张进城,郝跃,朱志炜;MOS结构中薄栅氧化层高场退火效应的研究[J];物理学报;2001年08期
6 刘红侠,郝跃,孙志;深亚微米MOS器件的热载流子效应[J];半导体学报;2001年06期
7 韩德栋,张国强,余学峰,任迪远;注F短沟MOSFET的沟道热载流子效应[J];半导体学报;2001年05期
8 张卫东,郝跃,汤玉生;深亚微米MOSFET热载流子退化机理及建模的研究进展[J];电子学报;1999年02期
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