基于FPGA的SCA芯片读出方法与电路研究

发布时间：2019-03-13 11:59

【摘要】：在核辐射测量中,粒子通过探测器时产生激发、电离、光电倍增等过程,探测器输出信号中包含粒子的许多物理信息。前端电子学与触发探测器和数据获取系统相连接,然而,随着现代粒子物理和核物理实验的发展,传统的前端电子学由于集成度低、成本高、采样速率低已经不能满足未来粒子物理与核物理实验发展的要求。国外已经出现了多款专为前端电子学设计的基于开关电容阵列(Switched Capacitor Array,SCA)的ASIC芯片,而国内基于SCA ASIC芯片的应用研究处于初期阶段。所以研究基于开关电容阵列ASIC芯片的采样原理和其在当代物理实验中的应用很有必要。本文针对目前国际上比较成熟的SCA芯片DRS4的采样技术,研究基于FPGA的SCA芯片读出方法和逻辑设计,并开发了一套专门用于阵列探测器的上位机数据采集控制与获取软件。拟开展以下几方面的工作:开展了针对SCA芯片DRS4的高速采样技术,在可编程逻辑器件FPGA内实现与DRS4接口模块、校准模块、ADC接口模块和时序逻辑模块的逻辑设计,以及实现与上位机的数据传输。设计了一套数据采集与控制上位机软件,软件在wx Widgets平台上进行开发,采用模块化设计思路和多线程技术,软件通过USB总线与前端电子学硬件部分通信。从软件架构、命令行接口模块、数据采集与获取模块、数据处理模块和图形用户界面几方面重点讨论了上位机软件的设计思路和设计方法。研究了实时采样中所用到的线性插值算法、非线性插值算法和正弦插值算法,并采用正弦波过零算法和直流偏置误差补偿算法分别实现了对时间的修正和幅度的校准。最后对DRS4原型样机进行了性能测试和相关修正算法验证测试,并和闪烁晶体阵列探测器进行了联调测试。经测试表明,本设计可以成功配合硬件满足系统的调试和测试工作。
[Abstract]:In nuclear radiation measurement, particles generate excitation, ionization, photomultiplier and other processes when they pass through the detector. The detector output signal contains a lot of physical information of the particle. Front-end electronics is connected to trigger detectors and data acquisition systems. However, with the development of modern particle physics and nuclear physics experiments, traditional front-end electronics have low integration and high costs. The low sampling rate can not meet the requirements of the future development of particle physics and nuclear physics experiments. There have been a number of ASIC chips designed for front-end electronics based on switched capacitor array (Switched Capacitor Array,SCA) in foreign countries, while the application research based on SCA ASIC chips in China is in the initial stage. So it is necessary to study the sampling principle based on switched capacitor array (ASIC) chip and its application in contemporary physics experiments. Aiming at the sampling technology of SCA chip DRS4, this paper studies the readout method and logic design of SCA chip based on FPGA, and develops a set of data acquisition control and acquisition software for upper computer specially used in array detector. The main work is as follows: the high-speed sampling technology for SCA chip DRS4 is carried out, and the logic design of DRS4 interface module, calibration module, ADC interface module and time sequence logic module is realized in programmable logic device (FPGA). And realize the data transmission with the upper computer. A set of software for data acquisition and control is designed. The software is developed on the platform of wx Widgets. The software communicates with the front-end electronics hardware through USB bus with modularization design idea and multi-thread technology. From the software architecture, command-line interface module, data acquisition and acquisition module, data processing module and graphical user interface, the design ideas and methods of upper computer software are discussed in detail. The linear interpolation algorithm, nonlinear interpolation algorithm and sine interpolation algorithm used in real-time sampling are studied. The time correction and amplitude calibration are realized by using sine wave zero-crossing algorithm and DC bias error compensation algorithm, respectively. Finally, the performance test and related correction algorithm verification of the DRS4 prototype are carried out, and the joint test with the scintillation crystal array detector is carried out. The test results show that this design can successfully cooperate with the debugging and testing work of the hardware satisfaction system.
【学位授予单位】：西北师范大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791;TN402

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