TFET单元库设计技术研究
[Abstract]:As a new type of low-power device, TFET adopts asymmetric doping in the source-drain region in physical structure, and controls the energy band offset by the external gate voltage, and then realizes the device work by using the tunneling breakdown principle. Compared with the traditional drift-diffusion mechanism MOSFET devices, the sub-threshold slope of TFET devices can break through the limit of 60m V/dec and achieve higher current-switching ratio at lower power supply voltage, thus achieving the goal of ultra-low power consumption. Digital standard cell library is the key of IC design automation and the bridge between front-end design and back-end physical implementation. Based on the traditional MOSFET technology, this paper explores the research direction of TFET application, and applies the TFET device to the design of digital standard cell library. On the basis of the existing technology, the TFET device model is used to do some research, and some achievements in cell design, layout planning and device detection are obtained. Based on the traditional technology of MOSFET device, the library is built, which includes the extraction and optimization of the schematic diagram of the library unit, the simulation of the characteristics and the drawing of the layout, and using the existing library unit to complete the whole process of building the library. Contains the most important types of library file generation and the corresponding script file writing. In the unit design, the combinatorial logic and the sequential logic circuit of the unit are deeply studied, and the influence of the transmission gate logic on the design of the whole circuit is analyzed based on the TFET device model. Then the circuit design structure suitable for TFET devices is compared and selected. In addition, according to the compatibility problem of the existing model, a double clock edge test circuit is designed for setting up time and holding time of the trigger circuit. In the aspect of layout planning, according to the layout model of flow sheet test and the design scheme of cell library, the layout planning of unit layout is carried out, and the layout detection of TFET devices is studied. The corresponding DRC detection rules are modified to detect the special structure of TFET devices including TFET devices for general types and special types of TFET devices including Pocket structures and Underlap structures.
【学位授予单位】:哈尔滨工业大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN386
【参考文献】
相关期刊论文 前10条
1 叶钟灵;;纪念摩尔定律50周年[J];电子产品世界;2015年08期
2 迟殿鑫;高新江;姚科明;陈伟;张承;;边缘击穿抑制对InGaAs/InP盖革模式APD性能的影响[J];半导体光电;2015年03期
3 ZHAN Zhan;HUANG QianQian;HUANG Ru;JIANG WenZhe;WANG YangYuan;;A comb-gate silicon tunneling field effect transistor with improved on-state current[J];Science China(Information Sciences);2013年07期
4 秋小强;杨海钢;周发标;谢元禄;;非线性延时模型及逻辑门优化设计[J];微电子学;2011年06期
5 陶然;;守望摩尔定律[J];电子产品世界;2010年06期
6 刘布民;蔡伟;陆铁军;王宗民;;低功耗无损电流检测技术的分析与设计[J];电子科技大学学报;2008年03期
7 卢俊;贾嵩;王源;张钢刚;;高性能的标准单元库设计[J];航空计算技术;2007年03期
8 张培勇;严晓浪;史峥;高根生;;超深亚微米与纳米级标准单元的可制造性设计与验证技术[J];电路与系统学报;2006年05期
9 杨媛;高勇;余宁梅;;超深亚微米CMOS工艺参数波动的测量电路[J];半导体学报;2006年09期
10 钟涛,王豪才;CMOS集成电路的功耗优化和低功耗设计技术[J];微电子学;2000年02期
,本文编号:2439531
本文链接:https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2439531.html