3D-IC中TSV的冗余布局与可测性结构优化方法研究
发布时间：2019-03-16 11:57
【摘要】：随着半导体技术的迅猛发展,集成芯片性能在摩尔定律的指导下不断提高,尤其是近年来3D集成芯片技术的出现更是在一定意义上打破了摩尔定律,实现了更高层次的集成性能。随着各大半导体公司逐步推出3D芯片系列产品,其测试方法引起学术界的广泛关注。尤其是TSV穿透硅通孔(Through Silicon Via)的出现,更引出了一系列测试问题,由于其成品率相对于现有的集成芯片技术较低,在测试方面更需要新的手段和技术。全文结构采用由底层研究向顶层研究的结构,从TSV的失效机理入手,研究其失效和修复,之后着眼于顶层整个3D-IC的可测性结构的方向。本文主要介绍了3D集成芯片测试的一些关键性问题。第一,针对TSV的失效,研究在制造过程中由于工艺缺陷而造成的各种TSV失效机理,针对失效后TSV的电学外特性进行RC电路的故障建模,运用Hspice仿真工具模拟典型故障的充放电过程,给出了具体的故障电压以及发生故障的位置不同引起的故障电压偏差。第二,针对TSV的硬故障设计TSV冗余结构,根据此冗余切换结构的特性进行区块内部的冗余TSV的数量分析,修复率分析以及成品率分析等等。并且在面积开销及时间开销等方面综合评价TSV冗余结构。通过TSV冗余数量和修复率对冗余结构进行综合分析,芯片成品率与冗余TSV数量直接相关,本文方法在面积和时间开销方面均有降低,结果表明这种TSV冗余结构能够覆盖绝大多数TSV故障并且将成品率提高到99%,这能够有效的降低成本。第三,针对测试结构及对应测试访问机制的优化,在前期研究中仿真实现了串行测试和并行测试两种结构后,综合考虑这两种测试方法的优点,在测试时间、硬件冗余、测试带宽和功耗示踪的温度四种条件限制下,以得到最小的测试负担系数为目标,对测试访问机制进行一种基于ILP思想的综合优化,即实现了基于混合封装策略的Df T设计,实验结果表明,该方法能够得到较小的测试负担系数,为测试访问机制的优化设计提供参考。
[Abstract]:With the rapid development of semiconductor technology, the performance of integrated chips has been improved under the guidance of Moore's law, especially in recent years, the appearance of 3D integrated chip technology has broken Moore's law in a certain sense. A higher level of integration performance is achieved. With the introduction of three-dimensional chip series by semiconductor companies, the testing methods have attracted wide attention in academia. Especially, the emergence of TSV through silicon-through-hole (Through Silicon Via) leads to a series of testing problems. Because of its low yield compared with the existing integrated chip technology, it needs more new methods and techniques in the field of testing. Based on the failure mechanism of TSV, the failure and repair of the full-text structure is studied, and then the direction of the testability structure of the whole top-level 3D-IC is focused on. This paper mainly introduces some key problems of 3D integrated chip testing. Firstly, aiming at the failure of TSV, the failure mechanism of TSV due to process defects in manufacturing process is studied, and the fault modeling of RC circuit is carried out according to the external electrical characteristics of TSV after failure. The charge-discharge process of typical fault is simulated by using Hspice simulation tool. The specific fault voltage and the fault voltage deviation caused by different fault location are given. Secondly, the redundancy structure of TSV is designed for the hard fault of TSV. According to the characteristics of the redundant switching structure, the quantity analysis, repair rate analysis and yield analysis of the redundant TSV within the block are carried out. At the same time, the redundancy structure of TSV is comprehensively evaluated in the aspects of area cost and time cost. The redundant structure is analyzed by the number of redundant TSV and the repair rate. The chip yield is directly related to the number of redundant TSV. The method in this paper has reduced both area and time overhead, and the chip yield is directly related to the number of redundant TSV. The results show that the TSV redundancy structure can cover the majority of TSV faults and increase the yield to 99%, which can effectively reduce the cost. Thirdly, aiming at the optimization of the test structure and the corresponding test access mechanism, after the serial test and parallel test are simulated and implemented in the previous research, the advantages of these two testing methods are considered comprehensively, such as test time, hardware redundancy, and so on. Under the four conditions of test bandwidth and power tracer temperature, in order to obtain the minimum test burden coefficient, a comprehensive optimization of test access mechanism based on ILP idea is carried out, that is, the design of Df T based on hybrid encapsulation strategy is realized. The experimental results show that the proposed method can obtain a small test burden coefficient, which provides a reference for the optimization design of the test access mechanism.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
本文编号：2441308
[Abstract]:With the rapid development of semiconductor technology, the performance of integrated chips has been improved under the guidance of Moore's law, especially in recent years, the appearance of 3D integrated chip technology has broken Moore's law in a certain sense. A higher level of integration performance is achieved. With the introduction of three-dimensional chip series by semiconductor companies, the testing methods have attracted wide attention in academia. Especially, the emergence of TSV through silicon-through-hole (Through Silicon Via) leads to a series of testing problems. Because of its low yield compared with the existing integrated chip technology, it needs more new methods and techniques in the field of testing. Based on the failure mechanism of TSV, the failure and repair of the full-text structure is studied, and then the direction of the testability structure of the whole top-level 3D-IC is focused on. This paper mainly introduces some key problems of 3D integrated chip testing. Firstly, aiming at the failure of TSV, the failure mechanism of TSV due to process defects in manufacturing process is studied, and the fault modeling of RC circuit is carried out according to the external electrical characteristics of TSV after failure. The charge-discharge process of typical fault is simulated by using Hspice simulation tool. The specific fault voltage and the fault voltage deviation caused by different fault location are given. Secondly, the redundancy structure of TSV is designed for the hard fault of TSV. According to the characteristics of the redundant switching structure, the quantity analysis, repair rate analysis and yield analysis of the redundant TSV within the block are carried out. At the same time, the redundancy structure of TSV is comprehensively evaluated in the aspects of area cost and time cost. The redundant structure is analyzed by the number of redundant TSV and the repair rate. The chip yield is directly related to the number of redundant TSV. The method in this paper has reduced both area and time overhead, and the chip yield is directly related to the number of redundant TSV. The results show that the TSV redundancy structure can cover the majority of TSV faults and increase the yield to 99%, which can effectively reduce the cost. Thirdly, aiming at the optimization of the test structure and the corresponding test access mechanism, after the serial test and parallel test are simulated and implemented in the previous research, the advantages of these two testing methods are considered comprehensively, such as test time, hardware redundancy, and so on. Under the four conditions of test bandwidth and power tracer temperature, in order to obtain the minimum test burden coefficient, a comprehensive optimization of test access mechanism based on ILP idea is carried out, that is, the design of Df T based on hybrid encapsulation strategy is realized. The experimental results show that the proposed method can obtain a small test burden coefficient, which provides a reference for the optimization design of the test access mechanism.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
【参考文献】
相关硕士学位论文 前1条
1 杨年宏;基于三维结构的SoC低功耗测试技术研究[D];合肥工业大学;2011年
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