基于HDL代码的数字电路性能评估与PAITS优化
发布时间：2019-04-04 12:40
【摘要】：提高源代码的质量是加快SoC/ASIC芯片设计进度、提高其质量的重要手段。而RTL综合器进行的综合工作与HDL源代码间的设计迭代,也是影响芯片设计进度重要环节。高质量的RTL代码可以得到更优的综合结果,减少在电路综合与HDL代码编写之间的设计迭代,从而缩短电路设计时间并提高设计效率。为了提高源代码的研发质量、尽早发现芯片设计阶段存在的缺陷,缩短电路设计迭代过程、提高电路设计效率,从而加速SoC/ASIC的设计过程,本文认为可以从以下两个方面入手:其一,开发出具有更好时序的HDL代码,为综合和最终布线完成后遗留较少的时序偏差问题,减少在门级需要解决的时序问题;其二,需要一种好的方法来优化门级电路,使得在可以的情况下尽可能不追溯到HDL代码以减少设计工作的迭代。本文分别为以上两种方案的设计与实现进行了研究,提出了基于HDL代码的数字电路静态时序分析和数字电路并行拓扑排序优化(PAITS)算法。本文的主要成果有:1.针对开发出具有更好时序的代码这一问题,提出了基于HDL代码的数字电路静态时序分析。HDL代码的数字电路静态时序分析进行在集成电路设计的编译仿真之后、逻辑综合之前,是通过根据代码预判电路结构、对门延时建模,从而达到分析电路时序情况的目的。本文使用树型结构分别对HDL代码中的纯组合逻辑语句和会综合出寄存器的语句进行时序路径建模,将电路中的每条时序路径建立为有输入和输出的顶点,指向顶点的边表示输入信号,从顶点出发的边为被赋值变量或电路输出,顶点的权值为路径的延时。然后通过对HDL代码中的语句进行延时建模,即可对电路中的各个路径给出了延时的预估。由此可以分析得到电路的关键路径及其延时,从而分析电路是否满足目标时序要求。实验结果显示,静态时序分析得到的电路关键路径,皆包含在本算法分析后找到的电路关键路径中,本方法预估的电路延时与STA分析结果的相对误差在30%内。2.针对当数字电路的时序难以满足优化目标时要进行设计迭代的问题,依据电路并行工作的特性,改进产生线性序列的拓扑排序算法,提出了并行全入度拓扑排序(PAITS),而后根据PAITS提出数字电路PAITS优化算法。该优化算法首先使用分析有向图的思想分析电路结构,对电路的有向图进行PAITS,得到电路中插入寄存器可选位置的详细信息,再根据排序得到的信息和优化目标,直接选择最佳位置,通过重写网表插入流水线、优化电路,无需设计迭代。且与有效重定时判定经典算法FEAS的时间复杂度O(|V|?|E|)相比,PAITS拥有较低的时间复杂度O(f?|V|+|E|),其中f为电路扇出约束。实验结果表明,插入同样级数的寄存器时,使用本算法优化的电路与重定时优化的电路相比电路面积较之少了20-40%。
[Abstract]:Improving the quality of source code is an important means to speed up the design progress and improve the quality of SoC/ASIC chip. The iteration between the synthesis work of RTL synthesizer and the source code of HDL is also an important link that affects the progress of chip design. The high-quality RTL code can get better synthesis results, reduce the design iteration between circuit synthesis and HDL code writing, thus shorten the circuit design time and improve the design efficiency. In order to improve the research and development quality of the source code, the defects in the chip design stage are discovered as soon as possible, the iterative process of circuit design is shortened, and the circuit design efficiency is improved, so as to accelerate the design process of SoC/ASIC. In this paper, we think we can start with the following two aspects: firstly, we can develop HDL code with better timing, which can reduce the timing problems that need to be solved at the gate level for the sake of fewer timing deviation problems left after synthesis and final wiring; Secondly, a good method is needed to optimize gate-level circuits so as not to trace back to the HDL code as far as possible so as to reduce the iteration of design work. In this paper, the design and implementation of the above two schemes are studied, and the static timing analysis of digital circuits based on HDL code and the parallel topology sorting optimization (PAITS) algorithm of digital circuits are proposed. The main results of this paper are as follows: 1. In order to solve the problem of developing code with better timing, the static timing analysis of digital circuit based on HDL code is proposed. After compiling and simulation of integrated circuit design, before logic synthesis, the static timing analysis of digital circuit based on HDL code is carried out. By pre-judging the structure of the circuit according to the code and modeling the gate delay, the purpose of analyzing the timing of the circuit is achieved. In this paper, the tree structure is used to model the sequential path of the pure combinatorial logic statements in HDL code and the statements that synthesize registers, and each sequential path in the circuit is established as a vertex with input and output. The edge pointing to the vertex represents the input signal, the edge starting from the vertex is assigned variable or circuit output, and the weight of vertex is the delay of path. Then the delay model of the statements in the HDL code can be used to estimate the delay of each path in the circuit. Therefore, the critical path and delay of the circuit can be analyzed, and then it can be analyzed whether the circuit can meet the requirement of the target timing. The experimental results show that the circuit critical paths obtained by static time series analysis are included in the circuit critical paths found after the analysis of this algorithm. The relative error between the circuit delay predicted by this method and the results of STA analysis is within 30%. In order to solve the problem of design iteration when the timing of digital circuit is difficult to meet the optimization objective, according to the characteristics of circuit parallel work, the topological sorting algorithm of generating linear sequence is improved, and the parallel total degree topological ranking (PAITS),) is proposed. Then, based on PAITS, a digital circuit PAITS optimization algorithm is proposed. The algorithm first analyzes the circuit structure using the idea of analyzing directed graph, carries on the PAITS, to the directed graph of the circuit to get the detailed information of the optional position of the insert register in the circuit, and then obtains the information according to the sort and the optimization goal. Directly select the best location by rewriting the mesh to insert pipelining, optimize the circuit without the need to design iterations. Compared with the time complexity O (| V |? | E |) of the classical algorithm FEAS, PAITS has a lower time complexity O (f? | V | E |), where f is a circuit fan-out constraint. The experimental results show that when the registers of the same series are inserted, the area of the circuit optimized by this algorithm is 20% less than that of the retiming optimized circuit.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN79
本文编号：2453820
[Abstract]:Improving the quality of source code is an important means to speed up the design progress and improve the quality of SoC/ASIC chip. The iteration between the synthesis work of RTL synthesizer and the source code of HDL is also an important link that affects the progress of chip design. The high-quality RTL code can get better synthesis results, reduce the design iteration between circuit synthesis and HDL code writing, thus shorten the circuit design time and improve the design efficiency. In order to improve the research and development quality of the source code, the defects in the chip design stage are discovered as soon as possible, the iterative process of circuit design is shortened, and the circuit design efficiency is improved, so as to accelerate the design process of SoC/ASIC. In this paper, we think we can start with the following two aspects: firstly, we can develop HDL code with better timing, which can reduce the timing problems that need to be solved at the gate level for the sake of fewer timing deviation problems left after synthesis and final wiring; Secondly, a good method is needed to optimize gate-level circuits so as not to trace back to the HDL code as far as possible so as to reduce the iteration of design work. In this paper, the design and implementation of the above two schemes are studied, and the static timing analysis of digital circuits based on HDL code and the parallel topology sorting optimization (PAITS) algorithm of digital circuits are proposed. The main results of this paper are as follows: 1. In order to solve the problem of developing code with better timing, the static timing analysis of digital circuit based on HDL code is proposed. After compiling and simulation of integrated circuit design, before logic synthesis, the static timing analysis of digital circuit based on HDL code is carried out. By pre-judging the structure of the circuit according to the code and modeling the gate delay, the purpose of analyzing the timing of the circuit is achieved. In this paper, the tree structure is used to model the sequential path of the pure combinatorial logic statements in HDL code and the statements that synthesize registers, and each sequential path in the circuit is established as a vertex with input and output. The edge pointing to the vertex represents the input signal, the edge starting from the vertex is assigned variable or circuit output, and the weight of vertex is the delay of path. Then the delay model of the statements in the HDL code can be used to estimate the delay of each path in the circuit. Therefore, the critical path and delay of the circuit can be analyzed, and then it can be analyzed whether the circuit can meet the requirement of the target timing. The experimental results show that the circuit critical paths obtained by static time series analysis are included in the circuit critical paths found after the analysis of this algorithm. The relative error between the circuit delay predicted by this method and the results of STA analysis is within 30%. In order to solve the problem of design iteration when the timing of digital circuit is difficult to meet the optimization objective, according to the characteristics of circuit parallel work, the topological sorting algorithm of generating linear sequence is improved, and the parallel total degree topological ranking (PAITS),) is proposed. Then, based on PAITS, a digital circuit PAITS optimization algorithm is proposed. The algorithm first analyzes the circuit structure using the idea of analyzing directed graph, carries on the PAITS, to the directed graph of the circuit to get the detailed information of the optional position of the insert register in the circuit, and then obtains the information according to the sort and the optimization goal. Directly select the best location by rewriting the mesh to insert pipelining, optimize the circuit without the need to design iterations. Compared with the time complexity O (| V |? | E |) of the classical algorithm FEAS, PAITS has a lower time complexity O (f? | V | E |), where f is a circuit fan-out constraint. The experimental results show that when the registers of the same series are inserted, the area of the circuit optimized by this algorithm is 20% less than that of the retiming optimized circuit.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN79
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