MOS器件界面态特性研究及其可靠性分析
发布时间：2019-05-11 10:43
【摘要】：自集成电路工艺发展到深亚微米技术以来,器件的可靠性问题已成为阻碍集成电路工艺水平沿着Moore定律继续延伸的主要困难之一。研究表明,在深亚微米MOS工艺中,器件的可靠性问题愈加凸显,除了尺寸减小导致电场增强之外,工艺的改进也会带来新的可靠性问题。由此,本文针对65nm工艺下MOS器件的退化特性等可靠性问题展开研究,并深入分析了电荷泵技术在1um MOS器件界面态密度测量中的作用。论文主要研究内容如下:1、电荷泵技术在1um MOS器件界面态密度测量中的作用。对界面态密度进行理论分析的结果表明,脉冲频率、幅值、源漏反偏电压和器件栅氧化层宽长比等参量,都会影响电荷泵技术测量的可靠性。当测量频率在10k Hz-6000k Hz范围内、反偏置电压在0.3V-1.5V之间、栅脉冲电压幅值大于3.0V、栅宽度与长度比W/L较大时,电荷泵技术才能准确测量出1um MOS器件的界面态密度值。2、热载流子效应对65nm MOS器件可靠性的影响。在加速应力条件下,研究了65nm MOS器件的HCI退化特性,并采用衬底/漏极电流比率模型进行HCI寿命预测。实验结果发现,热载流子效应对65nm三栅器件造成严重影响,将导致器件出现最大跨导阈值电压退化和恒定电流阈值电压退化。3、时间介质击穿效应对65nm MOS器件可靠性的影响。在加速应力条件下,测量了65nm MOS器件中的TDDB退化特性,并采用新型幂指数寿命计算模型进行TDDB寿命预测研究。结果表明,时间介质击穿效应对65nm MOS器件影响较小,然而电压与温度提高均可加快器件的TDDB退化。而且,在温度较低时,器件发生多次软击穿后会再出现硬击穿现象;在温度较高时,器件只发生硬击穿。综上所述,本文通过实验检测、模型与数据分析获得的结果,可为准确分析1um MOS器件的界面态密度,以及65nm MOS器件的HCI与TDDB退化机制提供依据。
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【学位授予单位】：暨南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
本文编号：2474427
[Abstract]:Since the development of integrated circuit technology to deep sub-micron technology, the reliability of devices has become one of the main difficulties to hinder the continuous extension of integrated circuit technology level along the Moore law. The results show that in the deep sub-micron MOS process, the reliability of the device becomes more and more prominent. Besides the electric field enhancement caused by the decrease of the size, the improvement of the process will also bring new reliability problems. Therefore, the reliability of MOS devices in 65nm process is studied in this paper, and the role of charge pump technology in the measurement of interface density of states of 1um MOS devices is deeply analyzed. The main contents of this thesis are as follows: 1. The role of charge pump technology in the measurement of interface state density of 1um MOS devices. The results of theoretical analysis of interface state density show that the reliability of charge pump measurement is affected by pulse frequency, amplitude, source leakage reverse bias voltage and gate oxide width to length ratio. When the measuring frequency is in the range of 10k Hz-6000k Hz, the inverse bias voltage is between 0.3V-1.5V, the amplitude of gate pulse voltage is greater than 3.0V, and the gate width and length ratio is larger than W / L. The charge pump technique can accurately measure the interface density of states of 1um MOS devices. 2. The effect of hot carrier effect on the reliability of 65nm MOS devices. The HCI degradation characteristics of 65nm MOS devices are studied under accelerated stress conditions. The substrate / drain current ratio model is used to predict the HCI lifetime. The experimental results show that the hot carrier effect has a serious impact on 65nm three-gate devices, which will lead to the maximum transconductivity threshold voltage degradation and constant current threshold voltage degradation. 3, the effect of time medium breakdown effect on the reliability of 65nm MOS devices. Under the condition of accelerated stress, the degradation characteristics of TDDB in 65nm MOS devices are measured, and a new power exponential life calculation model is used to predict the life of TDDB. The results show that the breakdown effect of time medium has little effect on 65nm MOS devices, but the increase of voltage and temperature can accelerate the degradation of TDDB. Moreover, when the temperature is low, the hard breakdown will occur again after many soft breakdown of the device, and only hard breakdown will occur when the temperature is high. To sum up, the results obtained by experimental detection, model and data analysis can provide a basis for the accurate analysis of the interface state density of 1um MOS devices and the degradation mechanism of HCI and TDDB of 65nm MOS devices.
【学位授予单位】：暨南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
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