高速低功耗SAR ADC的关键技术研究与系统设计
发布时间：2019-05-16 07:47
【摘要】：随着通信行业的发展,特别是在5G时代的来临之际,原有的通信设备性能已经不能满足不断增长的通信应用需求。这就促使通信设备必须向着能够提供更高的通信带宽,更快的数据传输速率的方向发展。另一方面,伴随着物联网与移动设备(如手机)等应用领域的发展,单一设备往往要同时具有传感,计算,通信等等功能,对芯片的功能集成度要求很高。在这些应用领域,集成电路不仅要满足性能方面的要求,更要满足功耗方面的要求。在CMOS工艺的快速发展的前提下,半导体特征尺寸正在逐步减小。在该过程中,数字集成电路与模拟集成电路相比,能够更好地在集成度,功耗和速度等方面受益。这使得数字集成电路能够更好地满足实际应用中在速度、功耗和集成度方面不断增长的需求,这也使得在电路层面对于信号的处理逐步从模拟端向数字端转移。模数转换器就是这样一种能将现实世界中的模拟信号转换为可被数字系统识别的数字信号的电路系统,其作为连接模拟世界与数字系统的桥梁,显得非常重要。模数转换器的性能往往会成为全部体系性能的瓶颈。本文主要通过对高速低功耗SAR ADC的结构和设计方法的研究,分析得出了在高速低功耗SAR ADC的设计中存在的主要问题。并在对已经存在的相关方面的技术进行深入剖析的基础上,针对之前的设计存在的不足之处,提出了改进型的分段预量化-旁路电容阵列式DAC和bootstrap电路。随后以这两种技术为基础使用40nm CMOS工艺设计了一种高速低功耗单通道SAR ADC并进行了流片验证,对本设计和其应用的相应的技术进行了验证。芯片测试结果显示本论文设计的ADC在1.2V供电电压,340MS/s采样速率情况下,ADC的有效位数为9.09bit,SFDR为73.55dB。
[Abstract]:With the development of the communication industry, especially with the advent of the 5G era, the performance of the original communication equipment can no longer meet the growing demand for communication applications. This makes the communication equipment must be able to provide higher communication bandwidth and faster data transmission rate. On the other hand, with the development of the Internet of things and mobile devices (such as mobile phones) and other application fields, a single device often has the functions of sensing, computing, communication and so on, which requires high functional integration of the chip. In these application fields, integrated circuits should not only meet the performance requirements, but also meet the requirements of power consumption. With the rapid development of CMOS process, the characteristic size of semiconductors is gradually decreasing. In this process, digital integrated circuits can benefit better in integration, power consumption and speed compared with analog integrated circuits. This makes the digital integrated circuit better meet the increasing demand of speed, power consumption and integration in practical applications, which also makes the signal processing gradually transfer from analog to digital at the circuit level. Analog-to-digital converter (ADC) is such a circuit system which can convert analog signal in real world into digital signal which can be recognized by digital system. It is very important to act as a bridge between analog world and digital system. The performance of A / D converter often becomes the bottleneck of all system performance. In this paper, the structure and design method of high speed and low power SAR ADC are studied, and the main problems in the design of high speed and low power SAR ADC are analyzed. Based on the in-depth analysis of the existing related technologies, and in view of the shortcomings of the previous design, an improved piecewise pre-quantification-bypass capacitor array DAC and bootstrap circuits are proposed. Then, based on these two technologies, a high speed and low power consumption single channel SAR ADC is designed by using 40nm CMOS process, and the chip verification is carried out, and the corresponding technology of this design and its application is verified. The chip test results show that under the condition of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09bit, and the ADC is 73.55dB. in the case of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09 bit and the SFDR is 73.55 dB.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
本文编号：2478131
[Abstract]:With the development of the communication industry, especially with the advent of the 5G era, the performance of the original communication equipment can no longer meet the growing demand for communication applications. This makes the communication equipment must be able to provide higher communication bandwidth and faster data transmission rate. On the other hand, with the development of the Internet of things and mobile devices (such as mobile phones) and other application fields, a single device often has the functions of sensing, computing, communication and so on, which requires high functional integration of the chip. In these application fields, integrated circuits should not only meet the performance requirements, but also meet the requirements of power consumption. With the rapid development of CMOS process, the characteristic size of semiconductors is gradually decreasing. In this process, digital integrated circuits can benefit better in integration, power consumption and speed compared with analog integrated circuits. This makes the digital integrated circuit better meet the increasing demand of speed, power consumption and integration in practical applications, which also makes the signal processing gradually transfer from analog to digital at the circuit level. Analog-to-digital converter (ADC) is such a circuit system which can convert analog signal in real world into digital signal which can be recognized by digital system. It is very important to act as a bridge between analog world and digital system. The performance of A / D converter often becomes the bottleneck of all system performance. In this paper, the structure and design method of high speed and low power SAR ADC are studied, and the main problems in the design of high speed and low power SAR ADC are analyzed. Based on the in-depth analysis of the existing related technologies, and in view of the shortcomings of the previous design, an improved piecewise pre-quantification-bypass capacitor array DAC and bootstrap circuits are proposed. Then, based on these two technologies, a high speed and low power consumption single channel SAR ADC is designed by using 40nm CMOS process, and the chip verification is carried out, and the corresponding technology of this design and its application is verified. The chip test results show that under the condition of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09bit, and the ADC is 73.55dB. in the case of 1.2V power supply voltage and 340MS/s sampling rate, the effective bit of ADC is 9.09 bit and the SFDR is 73.55 dB.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
【参考文献】
相关硕士学位论文 前1条
1 汪肖阳;高速低功耗SAR ADC的研究与设计[D];电子科技大学;2015年
，本文编号：2478131
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