一种S波段跳频源的设计
发布时间：2019-05-16 16:53
【摘要】：为某项目设计一款频率在2 GHz~3 GHz宽带跳频源,频率间隔为1 MHz,跳频点数为1 001点。该跳频源要求相位噪声小于-100 dBc@1 kHz,杂散优于60 dB。分析指标和软件仿真计算,采用HITTITE公司的HMC830锁相芯片来实现该设计方案。采用HITTITE公司的PLL仿真设计软件对环路滤波器进行优化设计后应用到实际电路中,使得该芯片在-55℃到+85℃均可稳定工作。通过外接串口通信控制模块,实现频率的跳变。最终该设计的实物测试相位噪声、杂散指标均优于目标值。测试得到该频率源相位噪声可达到-100 dBc/Hz@1 kHz,杂散指标能够达到-70 dB,具有工程应用价值
[Abstract]:For a project, a wideband frequency hopping source with a frequency of 2 GHz to 3 GHz is designed, with a frequency interval of 1 MHz and a frequency hopping number of 1 001. The frequency-hopping source requires that the phase noise be less than -100 dBc@1 kHz and the spur is better than 60 dB. The design scheme is realized by using the HMC830 phase-lock chip of the HITTITE company based on the analysis index and the software simulation calculation. The design of the loop filter by the PLL simulation design software of HITTITE is applied to the real circuit, so that the chip can work stably at -55 鈩，
本文编号：2478422
[Abstract]:For a project, a wideband frequency hopping source with a frequency of 2 GHz to 3 GHz is designed, with a frequency interval of 1 MHz and a frequency hopping number of 1 001. The frequency-hopping source requires that the phase noise be less than -100 dBc@1 kHz and the spur is better than 60 dB. The design scheme is realized by using the HMC830 phase-lock chip of the HITTITE company based on the analysis index and the software simulation calculation. The design of the loop filter by the PLL simulation design software of HITTITE is applied to the real circuit, so that the chip can work stably at -55 鈩，
本文编号：2478422
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