基于改进CORDIC算法的直接数字频率合成器研究
发布时间：2019-05-18 03:22
【摘要】：直接数字频率合成器简称为DDS,这是一种最近一些年才发展起来的新型的频率合成技术。这种技术依托于快速发展的集成电路技术,现代集成电路技术根据摩尔定律的预测在不断的进步,直接数字频率合成器在这个环境之下也受到越来越多的重视。这种频率合成技术比以前的传统频率合成技术分辨率更高,转换时间更快,噪声更低,所以在许多的电子系统当中被广泛的应用。相位累加器、相幅转换器、数模转换器和低通滤波器这几个部分构成了直接数字频率合成器。以前的直接数字频率合成器一般都是采用查找表ROM或者CORDIC算法来实现相幅转换器,这两种方法各有优点,现在一般采用的是CORDIC算法实现,这种方法电路比较简单,占用的存储容量也很小。本文提出的直接数字频率合成器使用的是查找表ROM和CORDIC算法结合使用,能够减小噪声、减小转换时间、提高SFDR。同时这种方法能够减少计算迭代的次数,从而减少硬件电路的资源消耗。本文采用相位累加器的位宽是32位,相位累加器输出截断之后是19位,高3位用来进行区块选择,接下来的7位用来进行查找表ROM寻址,低9位用于CORDIC算法的旋转计算。RTL级的代码实现进行仿真时,SFDR均能够达到113dB左右,有比较高的无杂散动态范围。本文的DDS有三种工作模式:斜坡模式,Profile模式和单频模式。本篇文章对直接数字合成器的许多方面进行了详细的介绍,包括其概念、国内外的发展状况、其基本的结构原理。然后是本文的主要工作点,也就是相位幅度转换器的改进。最后对本文提出的DDS进行了逻辑综合和后端物理设计。进行逻辑综合的时候采用的工艺库是中芯国际的SMIC 0.18μm 1.8V 1P6M CMOS库,逻辑综合之后的芯片单元的总数是36700个,31074个组合逻辑单元,5623个时序逻辑单元,6306063.20μm2的总面积。1235.3mW的动态功耗和465.65μW的静态功耗,总的功耗是1235.8mW。
[Abstract]:Direct digital frequency synthesizer (DDS,) is a new frequency synthesis technology which has only been developed in recent years. This technology relies on the rapid development of integrated circuit technology. According to Moore's law, modern integrated circuit technology is making continuous progress, and direct digital frequency synthesizer has been paid more and more attention in this environment. Compared with the previous traditional frequency synthesis technology, this frequency synthesis technology has higher resolution, faster conversion time and lower noise, so it is widely used in many electronic systems. Phase accumulator, phase amplitude converter, digital-to-analog converter and low-pass filter constitute direct digital frequency synthesizer. In the past, the direct digital frequency synthesizer generally used the look-up table ROM or CORDIC algorithm to realize the phase amplitude converter. These two methods have their own advantages. Now the direct digital frequency synthesizer is usually implemented by CORDIC algorithm. This method circuit is relatively simple. The storage capacity occupied is also very small. The direct digital frequency synthesizer proposed in this paper uses the combination of look-up table ROM and CORDIC algorithm, which can reduce noise, reduce conversion time and improve SFDR.. At the same time, this method can reduce the number of iterations, thus reducing the resource consumption of hardware circuits. In this paper, the bit width of the phase accumulator is 32 bits, the output of the phase accumulator is 19 bits, the high 3 bits are used for block selection, and the next 7 bits are used for ROM addressing of the lookup table. The low 9 bits are used in the rotation calculation of CORDIC algorithm. When the code implementation at RTL level is simulated, the SFDR can reach about 113dB, and has a high non-stray dynamic range. There are three working modes of DDS in this paper: slope mode, Profile mode and single frequency mode. In this paper, many aspects of direct digital synthesizer are introduced in detail, including its concept, development at home and abroad, and its basic structure and principle. Then there is the main working point of this paper, that is, the improvement of phase amplitude converter. Finally, the logic synthesis and back-end physical design of DDS proposed in this paper are carried out. The process library used in logic synthesis is SMIC 0.18 渭 m 1.8V 1P6M CMOS library. The total number of chip units after logic synthesis is 36700, 31074 combinational logic units and 5623 sequential logic units. The total area of 6306063.20 渭 m ~ 2. 1235.3 mW dynamic power consumption and 465.65 渭 W static power consumption, the total power consumption is 1235.8 MW.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN741
本文编号：2479630
[Abstract]:Direct digital frequency synthesizer (DDS,) is a new frequency synthesis technology which has only been developed in recent years. This technology relies on the rapid development of integrated circuit technology. According to Moore's law, modern integrated circuit technology is making continuous progress, and direct digital frequency synthesizer has been paid more and more attention in this environment. Compared with the previous traditional frequency synthesis technology, this frequency synthesis technology has higher resolution, faster conversion time and lower noise, so it is widely used in many electronic systems. Phase accumulator, phase amplitude converter, digital-to-analog converter and low-pass filter constitute direct digital frequency synthesizer. In the past, the direct digital frequency synthesizer generally used the look-up table ROM or CORDIC algorithm to realize the phase amplitude converter. These two methods have their own advantages. Now the direct digital frequency synthesizer is usually implemented by CORDIC algorithm. This method circuit is relatively simple. The storage capacity occupied is also very small. The direct digital frequency synthesizer proposed in this paper uses the combination of look-up table ROM and CORDIC algorithm, which can reduce noise, reduce conversion time and improve SFDR.. At the same time, this method can reduce the number of iterations, thus reducing the resource consumption of hardware circuits. In this paper, the bit width of the phase accumulator is 32 bits, the output of the phase accumulator is 19 bits, the high 3 bits are used for block selection, and the next 7 bits are used for ROM addressing of the lookup table. The low 9 bits are used in the rotation calculation of CORDIC algorithm. When the code implementation at RTL level is simulated, the SFDR can reach about 113dB, and has a high non-stray dynamic range. There are three working modes of DDS in this paper: slope mode, Profile mode and single frequency mode. In this paper, many aspects of direct digital synthesizer are introduced in detail, including its concept, development at home and abroad, and its basic structure and principle. Then there is the main working point of this paper, that is, the improvement of phase amplitude converter. Finally, the logic synthesis and back-end physical design of DDS proposed in this paper are carried out. The process library used in logic synthesis is SMIC 0.18 渭 m 1.8V 1P6M CMOS library. The total number of chip units after logic synthesis is 36700, 31074 combinational logic units and 5623 sequential logic units. The total area of 6306063.20 渭 m ~ 2. 1235.3 mW dynamic power consumption and 465.65 渭 W static power consumption, the total power consumption is 1235.8 MW.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN741
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