OTP逻辑阵列电路设计技术研究

发布时间：2019-05-30 08:01

【摘要】：随着微电子技术的快速发展,可编程逻辑阵列已经经历几次变革,从最初的PAL(Programmable Array Logic)到之后的PLA(Programmable Logic Array),再到现在使用最广泛的CPLD(Complex Programmable Logic Device)和FPGA(Field Programmable Gate Array)。随着大家对信息安全领域越来越重视,OTP(One Time Programmable)FPGA的研究也慢慢受到各个领域的青睐。但是由于OTP FPGA直接研究的复杂性以及困难性,国内很多研究者们从OTP逻辑阵列电路开始着手,旨在一步步的向前推进,最终研发出高性能的OTP FPGA。论文的目的是设计一款OTP逻辑阵列电路,旨在验证自主研究的新型OTP编程位元应用于实际电路的可行性。此次设计的电路主要包括编程位元结构的设计、外围可编程电路及仿真、回读测试电路及仿真、逻辑实现功能电路、整体版图设计以及芯片实物功能测试验证。通过对新型OTP编程位元击穿原理的介绍,提出了本次论文使用的新型的OTP编程位元的结构,并对其工作原理进行了详细说明,在基于该编程位元的结构上,提出了整个逻辑阵列的外围工作电路的设计方案。其中电压转换电路实现了高压信号被内部电路的安全读取。2级电荷泵电路将外部高压信号平稳安全的传递到编程位元端口,减少了因编程高压的不稳定导致编程位元编程性能的降低甚至失败。多级译码方式配合逻辑阵列的排布降低了整个电路工作延迟时间。读测试电路利用脉宽展宽电路通过对地址脉冲的展宽,配合灵敏放大器,实现对编程位元数据的正确读取,并配合两级DICE(Dual Interlocked Storage Cell)锁存器,将读取数据安全可靠的送出供外部读取。逻辑实现电路通过CLB(Configurable Logic Block)内部与编程位元的相连,实现了编程数据的读出,并根据外部需求实现相应的组合或时序功能。整体版图设计中,本文指出了一些特殊问题的注意事项,并对其提出了相应的解决方案,通过提取相应的寄生参数,利用后仿真工具进行后仿真,根据仿真结果,修改电路与版图,最终达到本次的设计目的。通过对流片回来后的芯片进行相应模块的功能测试,根据测试结果显示,本次设计的OTP逻辑阵列电路在编程、回读以及逻辑功能实现上均能正常的工作,满足预期的设计期望,达到了本次芯片设计的目的。
[Abstract]:With the rapid development of microelectronics technology, programmable logic array has undergone several changes, from the original PAL (Programmable Array Logic) to the later PLA (Programmable Logic Array), to the most widely used CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array). As people pay more and more attention to the field of information security, the research of, OTP (One Time Programmable) FPGA is gradually favored by various fields. However, due to the complexity and difficulty of OTP FPGA direct research, many domestic researchers start with OTP logic array circuits, aiming at advancing step by step, and finally developing high performance OTP FPGA.. The purpose of this paper is to design a OTP logic array circuit to verify the feasibility of applying the new OTP programming bit to the actual circuit. The circuit mainly includes the design of programming bit structure, peripheral programmable circuit and simulation, read back test circuit and simulation, logic realization function circuit, overall layout design and chip physical function test verification. Through the introduction of the breakdown principle of the new OTP programming bit, the structure of the new OTP programming bit used in this paper is put forward, and its working principle is explained in detail. The design scheme of the peripheral working circuit of the whole logic array is put forward. The voltage conversion circuit realizes the safe reading of the high voltage signal by the internal circuit. The 2 stage charge pump circuit transmits the external high voltage signal smoothly and safely to the programming bit port. Because of the instability of programming pressure, the performance of programming bit programming is reduced or even failed. The multistage decoding mode combined with the arrangement of logic array reduces the working delay time of the whole circuit. The reading test circuit uses the pulse width broadening circuit to realize the correct reading of the programming bit metadata and the two-stage DICE (Dual Interlocked Storage Cell) latch by broadening the address pulse and cooperating with the sensitive amplifier. The read data is sent out safely and reliably for external reading. The logic realization circuit is connected with the programming bit through the internal connection of CLB (Configurable Logic Block), which realizes the readout of programming data, and realizes the corresponding combination or timing function according to the external requirements. In the overall layout design, this paper points out some special problems for attention, and puts forward the corresponding solutions. By extracting the corresponding parasitic parameters, using post-simulation tools to carry out post-simulation, according to the simulation results, Modify the circuit and layout, and finally achieve the purpose of this design. Through the function test of the chip after the chip comes back, the test results show that the OTP logic array circuit can work normally in programming, readback and logic function realization, and meets the expected design expectations. The purpose of the chip design has been achieved.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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