基于可信设计流程的方法研究

发布时间：2019-06-11 13:30

【摘要】：随着我国集成电路行业的迅猛发展,以及集成电路产品日渐深入到我们的日常生活中,基于集成电路设计流程的可信性方法研究也成了前沿性的研究课题。可信性设计方法的研究主要涉及到设计流程和可信性两个方面,本文从集成电路的设计流程出发,分析了RTL级硬件木马的结构和工作特性,研究了贯穿整个设计流程的DFT技术,并提出了如何利用DFT技术来检测和判定硬件木马的位置。本文主要工作内容如下:第一,对硬件木马的结构特性以及工作特点进行了详细分析,并对当前已出现的硬件木马检测方法进行了分析、对比、归纳,然后列举了每种检测方法的优缺点。第二,深入研究了RTL级硬件木马的工作和结构特点,通过分析基于Verilog语言的RTL级硬件木马的结构特点,以及对AES基准电路的分析,建立了RTL级硬件木马检测的可信模型,并提出了利用Perl语言完成RTL级硬件木马的检测方法,并通过其他攻击者设计的木马进行了验证,该方法不仅简单有效而且弥补了传统检测方法和UCI检测方法的不足。第三,深入研究了可测性设计技术及其实施的各个阶段,提出了基于DFT技术的硬件木马检测方法。通过对基准电路插入扫描链前后的数据进行分析发现,扫描链的插入可以放大硬件木马的活动1.4倍以上;通过对不同工艺下扫描链激活前后的参数进行对比发现:在SMIC130nm工艺条件下扫描链的插入使木马检测准确率提高了65%,在SMIC90nm条件下提升了49%。最后详细分析了造成结果变化的原因并在此基础上进一步提出了硬件木马的定位方法。第四,更进一步的分析了基于DFT技术的硬件木马定位技术,首先阐述了实验的整个流程和使用的不同木马结构,然后通过添加不同数量的扫描链之后,分析局部激活和全局激活扫描链时对电路所带来的影响发现:单独激活含有木马的扫描链可以使电路的整体平均功耗增加1.7倍以上,峰值功耗增加1.8倍以上,并通过实验证明了可以通过该方式找到硬件木马所在的大概位置。
[Abstract]:With the rapid development of integrated circuit industry in our country and the deepening of integrated circuit products into our daily life, the research on credibility method based on integrated circuit design process has become a leading research topic. The research of credibility design method mainly involves two aspects: design flow and credibility. Based on the design flow of integrated circuit, this paper analyzes the structure and working characteristics of RTL level hardware Trojan horse, and studies the DFT technology that runs through the whole design process. How to use DFT technology to detect and determine the location of hardware Trojan horse is put forward. The main contents of this paper are as follows: first, the structural characteristics and working characteristics of the hardware Trojan horse are analyzed in detail, and the detection methods of the hardware Trojan horse are analyzed, compared and summarized. Then the advantages and disadvantages of each detection method are listed. Secondly, the work and structure characteristics of RTL level hardware Trojan horse are deeply studied. By analyzing the structural characteristics of RTL level hardware Trojan horse based on Verilog language and the analysis of AES reference circuit, the trusted model of RTL level hardware Trojan horse detection is established. The detection method of RTL level hardware Trojan horse is proposed and verified by other Trojans designed by other attackers. This method is not only simple and effective, but also makes up for the shortcomings of traditional detection methods and UCI detection methods. Thirdly, the testability design technology and its implementation stages are deeply studied, and the hardware Trojan horse detection method based on DFT technology is proposed. Through the analysis of the data before and after the reference circuit is inserted into the scanning chain, it is found that the insertion of the scan chain can amplify the activity of the hardware Trojan horse more than 1.4 times. By comparing the parameters before and after the activation of scanning chain under different processes, it is found that the insertion of scanning chain under SMIC130nm process improves the detection accuracy of Trojan horse by 65% and 49% under SMIC90nm condition. Finally, the causes of the change of results are analyzed in detail, and the location method of hardware Trojan horse is further put forward. Fourth, the hardware Trojan horse location technology based on DFT technology is further analyzed. Firstly, the whole process of the experiment and the different Trojan horse structures used are described, and then by adding different number of scanning chains, By analyzing the influence of local activation and global activation of scan chain on the circuit, it is found that activating the scan chain containing Trojan horse alone can increase the overall average power consumption of the circuit by more than 1.7 times and the peak power consumption by more than 1.8 times. The experimental results show that the approximate location of the hardware Trojan horse can be found by this method.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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