一种基于跟踪式量化器的高性能Delta-Sigma ADC的研究与实现
发布时间：2019-06-20 23:29
【摘要】：随着现代信息技术的高速发展以及移动终端设备的普及,高速、高精度和低功耗的信息处理设备成为市场的热门需求。Delta-Sigma ADC具有精度高、硬件开销低等特点被广泛使用在移动便携式设备中。但是Delta-Sigma ADC的速度受限问题成为制约其发展的瓶颈,因此如何提高其速度成为研究的热点。 本文在传统前馈结构多比特量化Delta-Sigma ADC的基础上,探索了基于跟踪式量化器的设计。与传统量化器不同,跟踪式量化器只量化当前输入和上次输入的残差,来有效降低量化器的输入摆幅,从而减少比较次数,降低功耗,提高转换速度,并在数字域中通过积分来恢复当前输入的大小。系统前馈结构的设计使得积分器只需要处理量化噪声,极大地降低了积分环路的信号摆幅。将量化比特数提高到8比特,进一步降低了量化噪声,从而进一步降低运放的设计要求降低功耗。数据加权平均技术被应用在反馈回路中减小多比特量化引起的非线性,从而保证系统的信号噪声失真比不降低(Signal to Noise and Distortion Ratio, SNDR).通过数学计算和Matlab建模仿真确定系统架构,并总结了一套完整的设计方法。考虑实际电路中的各种非理想因数,比如：运放的有限带宽、压摆率和直流增益等,并且分别对它们进行建模,再带入系统中进行仿真,最终为实际电路的参数设计提供依据。 8位跟踪式ADC中的DAC采用单调开关结构不仅节省了50%的电容,而且大幅降低了功耗。文中对传统双尾电流管结构的比较器进行了改进使其具有更低的失调电压和噪声,并且该结构只需要单相时钟控制,因此改进后的比较器也降低了对时钟产生电路的要求。在0.6V下采样开关采用自举技术不仅可以提高采样开关的线性度还可以增大允许的输入信号摆幅。本文还对传统的自举开关电路进行了优化,用PMOS管代替传统结构中的NMOS管,避免使用电容结构的电荷倍压器所带来的高功耗和大面积。 该款Delta-Sigma ADC采用了TSMC130m1P8M的标准CMOS工艺,工作在0.6V电压下,带宽为50kHz,过采样率为16,SNDR达到了76.8dB,核心电路的功耗为152.2μW,品质因数(Figure of Merit,FoM)为0.26pJ/step。芯片核心面积为0.25mm2。
[Abstract]:With the rapid development of modern information technology and the popularity of mobile terminal equipment, high-speed, high-precision and low-power information processing equipment has become a hot demand in the market. Delta-Sigma ADC is widely used in mobile portable devices because of its high precision and low hardware overhead. However, the speed constraint of Delta-Sigma ADC has become the bottleneck of its development, so how to improve its speed has become the focus of research. Based on the traditional feedforward structure multi-bit quantitative Delta-Sigma ADC, the design of tracking-based quantizer is explored in this paper. Different from the traditional quantizer, the tracking quantizer only quantifies the residual between the current input and the last input, so as to effectively reduce the input swing of the quantizer, thus reducing the number of comparisons, reducing power consumption, improving the conversion speed, and restoring the current input size through integration in the digital domain. The design of the feedforward structure of the system makes the Integrator only need to deal with the quantitative noise, which greatly reduces the signal swing of the integral loop. The quantized bit number is increased to 8 bits, and the quantization noise is further reduced, thus the design requirements of operational amplifier are further reduced to reduce the power consumption. The data weighted average technique is applied to the feedback loop to reduce the nonlinear caused by multi-bit quantification, so as to ensure that the signal noise distortion ratio of the system does not reduce the (Signal to Noise and Distortion Ratio, SNDR). The system architecture is determined by mathematical calculation and Matlab modeling and simulation, and a set of complete design methods are summarized. Considering all kinds of non-ideal factors in the actual circuit, such as the limited bandwidth, pendulum rate and DC gain of the operational amplifier, and modeling them respectively, and then bringing them into the system for simulation, finally providing the basis for the parameter design of the actual circuit. The monotone switching structure of DAC in 8-bit tracking ADC not only saves 50% capacitance, but also greatly reduces power consumption. In this paper, the comparator of the traditional double-tailed current tube structure is improved to have lower misalignment voltage and noise, and the structure only needs single-phase clock control, so the improved comparator also reduces the requirement of clock generation circuit. At 0.6 V, the bootstrap technique can not only improve the linearity of the sampling switch, but also increase the allowable swing of the input signal. The traditional bootstrap switch circuit is also optimized in this paper. PMOS transistor is used instead of NMOS transistor in traditional structure to avoid the high power consumption and large area caused by the charge multiplier with capacitance structure. The Delta-Sigma ADC adopts the standard CMOS process of TSMC130m1P8M, operating at 0.6 V voltage, the bandwidth is 50 Hz, the over-sampling rate is 16, the SNDR reaches 76.8dB, the power consumption of the core circuit is 152.2 渭 W, and the quality factor (Figure of Merit,FoM is 0.26pJ 鈮，
本文编号：2503602
[Abstract]:With the rapid development of modern information technology and the popularity of mobile terminal equipment, high-speed, high-precision and low-power information processing equipment has become a hot demand in the market. Delta-Sigma ADC is widely used in mobile portable devices because of its high precision and low hardware overhead. However, the speed constraint of Delta-Sigma ADC has become the bottleneck of its development, so how to improve its speed has become the focus of research. Based on the traditional feedforward structure multi-bit quantitative Delta-Sigma ADC, the design of tracking-based quantizer is explored in this paper. Different from the traditional quantizer, the tracking quantizer only quantifies the residual between the current input and the last input, so as to effectively reduce the input swing of the quantizer, thus reducing the number of comparisons, reducing power consumption, improving the conversion speed, and restoring the current input size through integration in the digital domain. The design of the feedforward structure of the system makes the Integrator only need to deal with the quantitative noise, which greatly reduces the signal swing of the integral loop. The quantized bit number is increased to 8 bits, and the quantization noise is further reduced, thus the design requirements of operational amplifier are further reduced to reduce the power consumption. The data weighted average technique is applied to the feedback loop to reduce the nonlinear caused by multi-bit quantification, so as to ensure that the signal noise distortion ratio of the system does not reduce the (Signal to Noise and Distortion Ratio, SNDR). The system architecture is determined by mathematical calculation and Matlab modeling and simulation, and a set of complete design methods are summarized. Considering all kinds of non-ideal factors in the actual circuit, such as the limited bandwidth, pendulum rate and DC gain of the operational amplifier, and modeling them respectively, and then bringing them into the system for simulation, finally providing the basis for the parameter design of the actual circuit. The monotone switching structure of DAC in 8-bit tracking ADC not only saves 50% capacitance, but also greatly reduces power consumption. In this paper, the comparator of the traditional double-tailed current tube structure is improved to have lower misalignment voltage and noise, and the structure only needs single-phase clock control, so the improved comparator also reduces the requirement of clock generation circuit. At 0.6 V, the bootstrap technique can not only improve the linearity of the sampling switch, but also increase the allowable swing of the input signal. The traditional bootstrap switch circuit is also optimized in this paper. PMOS transistor is used instead of NMOS transistor in traditional structure to avoid the high power consumption and large area caused by the charge multiplier with capacitance structure. The Delta-Sigma ADC adopts the standard CMOS process of TSMC130m1P8M, operating at 0.6 V voltage, the bandwidth is 50 Hz, the over-sampling rate is 16, the SNDR reaches 76.8dB, the power consumption of the core circuit is 152.2 渭 W, and the quality factor (Figure of Merit,FoM is 0.26pJ 鈮，
本文编号：2503602
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