基于SMIC 65nm工艺的静态随机存储芯片的后端设计
发布时间：2019-06-26 12:45
【摘要】：随着移动互联网技术的发展,片上系统的速度不断提高,推动了高速缓存对速度的需求。作为高速缓存的核心部件,静态随机存储器便成为了系统速度提升和功耗降低的关键。而且集成电路芯片的更新速度逐步加快,工程师们迫切希望缩短从最初设计到最终进入市场的时间,传统的基于管级的全定制设计方法就不能满足这一需求,而基于门级的半定制设计方法便成为集成电路设计领域中的主流。在半定制设计中最重要的革新环节就是后端设计,并且该项工作已成为各个公司和研究所的重点研究课题。集成电路的技术水平已经进入到深亚微米阶段,工程师在其后端设计领域中逐渐面临着越来越多的问题和越来越严重的挑战。例如,芯片特征尺寸的逐渐缩小导致互连效应问题的出现;芯片规模的不断增大导致运行时间急剧膨胀,极大影响了设计流程的迭代效率;信号完整性分析成为一项必需工作,给芯片的时序收敛带来影响;芯片线宽的一再缩小,导致互连线的噪声干扰开始影响芯片的整体工作速度和功能的实现;由于存在多个设计变量,而且它们相互依赖,导致时序收敛变得极其复杂;电压降和电迁移问题给芯片的工作性能带来功耗影响。因此在后端设计中工程师需要深入物理设计,结合电路特点,选取有效的EDA工具,研发出有针对性的后端设计流程。论文首先简单介绍了当前集成电路的发展状况以及国内外研究现况,从设计方法出发,引出专用集成电路设计的两种基本方法(展平式设计方法和硅虚拟原型设计方法),以及本次设计所采用Cadence公司的SoC Encounter仿真工具进行后端设计的流程。在阐述布局布线理论的基础之上,对天线效应和串扰问题的产生原因及其解决方案进行了分析和研究,并成功将芯片布线布通。对时钟树综合理论进行了深入分析,建立了合理的时钟树,使芯片的时序达到平衡。最后进行了静态时序分析、时序优化以及物理验证(DRC和LVS检查)的工作,完成了后端设计的全部流程。在以上各个设计流程设计的基础上,成功研发出本项目的后端设计方案,通过最终仿真和验证结果表明,该芯片的性能指标如下:工作频率达到166.6MZH-166.7MHZ,规模是800万门,流片面积为5050um×5050um,实现了存储速度快、低功耗、面积小等特点。该静态随机存储芯片已于2014年11月在北京成功流片。
[Abstract]:With the development of mobile Internet technology, the speed of on-chip system is increasing, which promotes the speed demand of cache. As the core component of cache, static random access memory (RAM) has become the key to improve the speed and reduce the power consumption of the system. Moreover, the updating speed of integrated circuit chips is gradually accelerated, and engineers are eager to shorten the time from initial design to final entry into the market. The traditional full customization design method based on tube level can not meet this demand, and the semi-custom design method based on gate level has become the mainstream in the field of integrated circuit design. The most important innovation in semi-custom design is back-end design, and this work has become the key research topic of various companies and research institutes. The technical level of integrated circuits has entered the deep submicron stage, and engineers are gradually facing more and more problems and more serious challenges in the field of back-end design. For example, the gradual reduction of chip feature size leads to the emergence of interconnection effect; the continuous increase of chip size leads to the rapid expansion of running time, which greatly affects the iterative efficiency of the design process; signal integrity analysis has become a necessary work, which has an impact on the timing convergence of the chip; the line width of the chip is reduced again and again, resulting in the noise interference of the interconnect line begins to affect the overall working speed and function of the chip. Due to the existence of multiple design variables and their interdependence, timing convergence becomes extremely complex, and voltage drop and electromigration problems affect the performance of the chip. Therefore, in the back-end design, engineers need to go deep into the physical design, combined with the circuit characteristics, select effective EDA tools, and develop a targeted back-end design process. Firstly, this paper briefly introduces the development of integrated circuits and the research status at home and abroad. From the design method, two basic methods of special purpose integrated circuit design (flattened design method and silicon virtual prototype design method) are introduced, and the process of back-end design using SoC Encounter simulation tool of Cadence company is introduced. On the basis of expounding the theory of layout and routing, the causes and solutions of antenna effect and crosstalk problem are analyzed and studied, and the chip wiring is successfully distributed. The clock tree synthesis theory is deeply analyzed, and a reasonable clock tree is established to balance the timing of the chip. Finally, the static timing analysis, timing optimization and physical verification (DRC and LVS inspection) are carried out, and the whole process of back-end design is completed. On the basis of the above design flow design, the back-end design scheme of the project is successfully developed. The final simulation and verification results show that the performance index of the chip is as follows: the working frequency is 166.6 MZH 鈮，
本文编号：2506188
[Abstract]:With the development of mobile Internet technology, the speed of on-chip system is increasing, which promotes the speed demand of cache. As the core component of cache, static random access memory (RAM) has become the key to improve the speed and reduce the power consumption of the system. Moreover, the updating speed of integrated circuit chips is gradually accelerated, and engineers are eager to shorten the time from initial design to final entry into the market. The traditional full customization design method based on tube level can not meet this demand, and the semi-custom design method based on gate level has become the mainstream in the field of integrated circuit design. The most important innovation in semi-custom design is back-end design, and this work has become the key research topic of various companies and research institutes. The technical level of integrated circuits has entered the deep submicron stage, and engineers are gradually facing more and more problems and more serious challenges in the field of back-end design. For example, the gradual reduction of chip feature size leads to the emergence of interconnection effect; the continuous increase of chip size leads to the rapid expansion of running time, which greatly affects the iterative efficiency of the design process; signal integrity analysis has become a necessary work, which has an impact on the timing convergence of the chip; the line width of the chip is reduced again and again, resulting in the noise interference of the interconnect line begins to affect the overall working speed and function of the chip. Due to the existence of multiple design variables and their interdependence, timing convergence becomes extremely complex, and voltage drop and electromigration problems affect the performance of the chip. Therefore, in the back-end design, engineers need to go deep into the physical design, combined with the circuit characteristics, select effective EDA tools, and develop a targeted back-end design process. Firstly, this paper briefly introduces the development of integrated circuits and the research status at home and abroad. From the design method, two basic methods of special purpose integrated circuit design (flattened design method and silicon virtual prototype design method) are introduced, and the process of back-end design using SoC Encounter simulation tool of Cadence company is introduced. On the basis of expounding the theory of layout and routing, the causes and solutions of antenna effect and crosstalk problem are analyzed and studied, and the chip wiring is successfully distributed. The clock tree synthesis theory is deeply analyzed, and a reasonable clock tree is established to balance the timing of the chip. Finally, the static timing analysis, timing optimization and physical verification (DRC and LVS inspection) are carried out, and the whole process of back-end design is completed. On the basis of the above design flow design, the back-end design scheme of the project is successfully developed. The final simulation and verification results show that the performance index of the chip is as follows: the working frequency is 166.6 MZH 鈮，
本文编号：2506188
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