SHA-less型流水线ADC的误差分析及校准技术研究
发布时间：2019-06-28 18:01
【摘要】：模数转换器(ADC)是模拟信号和数字信号处理系统的纽带,随着无线通讯快速发展,对ADC的要求也越来越高,人们希望在提升ADC的速度和精度的同时,尽可能的降低功耗。流水线ADC由于其流水的工作模式和特有的冗余位校正算法,在高速高精度的场合有广泛应用,但流水线ADC较大的功耗成为其很严重的缺陷。无前端采样保持电路(SHA-less)的流水线ADC可以节省大量的功耗,但也引入了一个严重的问题:ADC的第一级量化器要完成采样保持的功能,由MDAC和Sub-ADC同时采样动态的输入信号,由于这两个采样通道之间不可避免的存在失配,再加上时钟信号自身的影响,就导致了采样失配误差。这个误差是SHA-less型流水线ADC必须解决的问题,尤其是对于中频(IF)采样应用,因为它严重恶化了ADC的高频性能。本文所做的研究就致力于对这种流水线结构进行误差分析和针对采样失配误差进行校正。论文分析了SHA-less型流水线ADC各种误差源,包括噪声,采样保持电路误差,运放误差,Sub-ADC的误差以及电容失配导致的误差,以及SHA-less型流水线ADC特有的采样失配误差。论文结合一种基于tsmc 65nm实现的,12位SHA-less型高速流水线ADC,从三个方面分析了高速高精度的SHA-less流水线ADC主要的误差源。分析了比较器的失调电压,介绍了失调消除技术,最终确定了本设计所采用的三级预防大加锁存器的低失调比较器结构,其中融合了输入输出失调消除技术。然后对电路的电容失配和热噪声进行了详细的分析,并分别根据电路线性度和量化噪声的约束,得到电路各电容的限制条件,并最终确定了电容的大小。最后着重分析了SHA-less流水线ADC中固有的Sub-ADC和MDAC之间的采样失配误差,采样时刻偏差和采样网络带宽失配是产生采样失配误差的原因,本文定量分析了这两种误差的影响,得出结论;采样网络带宽失配在高频时可以等效为一定大小采样时刻偏差,而采样时刻偏差导致的采样误差与输入信号频率成正比。对未经过校准的12位250M流水线ADC进行仿真发现,当正弦输入信号频率从11MHz增加到261MHz时,其SNDR从73.6dB下降到56.3dB,SFDR从88.7dB下降到56.5dB。仿真结果与分析结论一致,采样失配误差严重恶化了ADC的高频性能。本文采用一种数字后台校准算法来解决这一问题。本文采用的采样失配误差校准模块包含三个电路单元,分别是:溢出检测单元、数字控制单元、可变延时单元。溢出检测单元检测第一流水线级的输出结果,将比较结果输入数字控制单元,数字控制单元产生延时调节控制码,产生的控制码作为可变延时单元的输入用来调节子ADC的采样信号延时,通过多次迭代,使得子ADC的采样时刻和MDAC采样时刻对齐,整个模数转换器可获得良好的高频性能。仿真结果显示,数字校准算法有效抑制了输入高频信号时严重的奇次谐波,改善了ADC的高频性能,使输入信号频率261MHz时,电路的SNDR提高到68.7dB,SFDR提高到77dB。在4倍内奎斯特频率(600M)处,依然能够保持60dB以上的SNDR,以及74dB的SFDR。经过校准的SHA-less结构ADC具有良好的中频采样性能。2.5V模拟电压1.2V数字电压下,整个校准电路功耗3.1mW。本设计可校准的最大采样时刻偏差可达到250ps,对于高速应用的流水线ADC来说,已经足够了。
[Abstract]:The analog-to-digital converter (ADC) is a link between the analog signal and the digital signal processing system. With the rapid development of the wireless communication, the requirements of the ADC are getting higher and higher, and it is desirable to reduce the power consumption as much as possible while improving the speed and accuracy of the ADC. The pipeline ADC has wide application in high-speed and high-precision applications due to its running mode and its unique redundancy bit correction algorithm, but the power consumption of the pipeline ADC is a very serious defect. a pipelined adc without a front-end sample-and-hold circuit (sha-less) can save a significant amount of power, but also introduces a serious problem: the first stage quantizer of the adc is to complete the function of the sample-hold, and the mdac and the sub-adc sample the dynamic input signal at the same time, Due to the inevitable mismatch between the two sampling channels, and the effect of the clock signal itself, the sample mismatch error is caused. This error is a problem that the SHA-less pipeline ADC must address, especially for intermediate frequency (IF) sampling applications, as it severely degrades the high frequency performance of the ADC. The research of this paper is devoted to the error analysis of such a pipeline and the correction of the error of the sample mismatch. The paper analyzes the various error sources of the SHA-less pipeline ADC, including the noise, the sample and hold circuit error, the operational amplifier error, the error of the Sub-ADC and the error caused by the capacitance mismatch, and the sample mismatch error characteristic of the SHA-less pipeline ADC. In this paper, a 12-bit SHA-less high-speed pipeline ADC based on tsmc 65 nm is combined, and the main error source of high-speed high-precision SHA-less pipeline ADC is analyzed from three aspects. The offset voltage of the comparator is analyzed, the offset cancellation technique is introduced, and the low-offset comparator structure of the three-stage prevention large-lock latch adopted in the design is finally determined, and the input-output offset cancellation technology is fused. And then the capacitance mismatch and the thermal noise of the circuit are analyzed in detail, and the limiting conditions of each capacitor of the circuit are obtained according to the linear degree of the circuit and the constraint of the quantization noise respectively, and the size of the capacitor is finally determined. In the end, the error of the sampling mismatch between the sub-ADC and the MDAC, which is inherent in the SHA-less pipeline ADC, is analyzed, and the sampling time deviation and the sample network bandwidth mismatch are the cause of the sampling mismatch error. The sampling network bandwidth mismatch can be equivalent to a certain size sampling time deviation at high frequency, and the sampling error caused by the sampling time deviation is directly proportional to the input signal frequency. It was found that the SNDR from 73.6 dB to 56.3 dB and the SFDR decreased from 88.7 dB to 56.5 dB when the frequency of the sinusoidal input signal increased from 11 MHz to 261 MHz. The result of the simulation is consistent with the analysis conclusion, and the sample mismatch error seriously deteriorates the high-frequency performance of the ADC. In this paper, a digital background calibration algorithm is used to solve this problem. The sample-mismatch error calibration module used in this paper consists of three circuit units, namely an overflow detection unit, a digital control unit and a variable delay unit. the overflow detection unit detects the output result of the first pipeline stage, the comparison result is input into the digital control unit, the digital control unit generates a time delay regulation control code, the generated control code is used as the input of the variable delay unit to adjust the sampling signal delay of the sub-ADC, So that the sampling time of the sub-ADC and the MDAC sampling time are aligned, and the whole analog-to-digital converter can obtain good high-frequency performance. The simulation results show that the digital calibration algorithm can effectively suppress the serious odd harmonics when the high-frequency signal is input, and the high-frequency performance of the ADC is improved. When the input signal frequency is 261MHz, the SNDR of the circuit is increased to 68.7 dB, and the SFDR is increased to 77 dB. The SNDR of more than 60 dB and the SFDR of 74 dB can still be maintained at 4 times the Nyquist frequency (600M). The calibrated SHA-less structure ADC has a good intermediate frequency sampling performance. The entire calibration circuit consumes 3.1 mW at a 2.5 V analog voltage of 1.2 V digital voltage. The maximum sampling time deviation of this design can be calibrated to 250 ps, which is sufficient for pipelined ADCs for high-speed applications.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
[Abstract]:The analog-to-digital converter (ADC) is a link between the analog signal and the digital signal processing system. With the rapid development of the wireless communication, the requirements of the ADC are getting higher and higher, and it is desirable to reduce the power consumption as much as possible while improving the speed and accuracy of the ADC. The pipeline ADC has wide application in high-speed and high-precision applications due to its running mode and its unique redundancy bit correction algorithm, but the power consumption of the pipeline ADC is a very serious defect. a pipelined adc without a front-end sample-and-hold circuit (sha-less) can save a significant amount of power, but also introduces a serious problem: the first stage quantizer of the adc is to complete the function of the sample-hold, and the mdac and the sub-adc sample the dynamic input signal at the same time, Due to the inevitable mismatch between the two sampling channels, and the effect of the clock signal itself, the sample mismatch error is caused. This error is a problem that the SHA-less pipeline ADC must address, especially for intermediate frequency (IF) sampling applications, as it severely degrades the high frequency performance of the ADC. The research of this paper is devoted to the error analysis of such a pipeline and the correction of the error of the sample mismatch. The paper analyzes the various error sources of the SHA-less pipeline ADC, including the noise, the sample and hold circuit error, the operational amplifier error, the error of the Sub-ADC and the error caused by the capacitance mismatch, and the sample mismatch error characteristic of the SHA-less pipeline ADC. In this paper, a 12-bit SHA-less high-speed pipeline ADC based on tsmc 65 nm is combined, and the main error source of high-speed high-precision SHA-less pipeline ADC is analyzed from three aspects. The offset voltage of the comparator is analyzed, the offset cancellation technique is introduced, and the low-offset comparator structure of the three-stage prevention large-lock latch adopted in the design is finally determined, and the input-output offset cancellation technology is fused. And then the capacitance mismatch and the thermal noise of the circuit are analyzed in detail, and the limiting conditions of each capacitor of the circuit are obtained according to the linear degree of the circuit and the constraint of the quantization noise respectively, and the size of the capacitor is finally determined. In the end, the error of the sampling mismatch between the sub-ADC and the MDAC, which is inherent in the SHA-less pipeline ADC, is analyzed, and the sampling time deviation and the sample network bandwidth mismatch are the cause of the sampling mismatch error. The sampling network bandwidth mismatch can be equivalent to a certain size sampling time deviation at high frequency, and the sampling error caused by the sampling time deviation is directly proportional to the input signal frequency. It was found that the SNDR from 73.6 dB to 56.3 dB and the SFDR decreased from 88.7 dB to 56.5 dB when the frequency of the sinusoidal input signal increased from 11 MHz to 261 MHz. The result of the simulation is consistent with the analysis conclusion, and the sample mismatch error seriously deteriorates the high-frequency performance of the ADC. In this paper, a digital background calibration algorithm is used to solve this problem. The sample-mismatch error calibration module used in this paper consists of three circuit units, namely an overflow detection unit, a digital control unit and a variable delay unit. the overflow detection unit detects the output result of the first pipeline stage, the comparison result is input into the digital control unit, the digital control unit generates a time delay regulation control code, the generated control code is used as the input of the variable delay unit to adjust the sampling signal delay of the sub-ADC, So that the sampling time of the sub-ADC and the MDAC sampling time are aligned, and the whole analog-to-digital converter can obtain good high-frequency performance. The simulation results show that the digital calibration algorithm can effectively suppress the serious odd harmonics when the high-frequency signal is input, and the high-frequency performance of the ADC is improved. When the input signal frequency is 261MHz, the SNDR of the circuit is increased to 68.7 dB, and the SFDR is increased to 77 dB. The SNDR of more than 60 dB and the SFDR of 74 dB can still be maintained at 4 times the Nyquist frequency (600M). The calibrated SHA-less structure ADC has a good intermediate frequency sampling performance. The entire calibration circuit consumes 3.1 mW at a 2.5 V analog voltage of 1.2 V digital voltage. The maximum sampling time deviation of this design can be calibrated to 250 ps, which is sufficient for pipelined ADCs for high-speed applications.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
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