基于SOI硅磁敏三极管差分结构集成化研究
发布时间：2019-07-01 15:32
【摘要】：本文通过分析平面结构硅磁敏三极管基本结构、工作原理和特性,给出集成化SOI硅磁敏三极管差分结构,该集成化结构由两个具有相反磁敏感方向的SOI硅磁敏三极管(PSMST1、PSMST2)和集电极负载电阻(RL1、RL2)构成,包括一个发射极(E)、两个基极(B1、B2)、两个集电极(C1、C2)和两个集电极负载电阻。根据基本结构,采用ATLAS软件构建平面硅磁敏三极管仿真模型,研究基区长度(L)、基区宽度(w)、发射区宽度(WE)和衬底类型对其IC-VCE特性、磁特性和温度特性的影响,实现结构参数优化,在此基础上,构建SOI硅磁敏三极管差分结构仿真模型进行仿真分析。基于上述,本文在器件层为100晶向P型高阻(ρ1000?·cm)SOI片上研究、设计并制作集成化SOI硅磁敏三极管差分结构。通过使用半导体参数测试仪(Keithley 4200)、磁场发生器系统(CH-100)、万用表(Agilent 34401A)、恒流源(Rigol SD120)、恒压源(Rigol DP832)以及高低温试验箱(Obis GDJS-100LG-G)等实验仪器,对不同几何结构尺寸的集成化SOI硅磁敏三极管差分结构芯片进行IC-VCE特性、磁特性和温度特性测试。根据实验结果,选出本文最优几何结构尺寸,即WE、w和L分别为400μm、50μm和100μm,当VDD=3.5 V,IB=0.5 mA时,SOI硅磁敏三极管和SOI硅磁敏三极管差分结构集成化芯片的集电极电压输出绝对磁灵敏度分别为68.97 mV/T和132.72 mV/T,集电极电压输出相对温度系数分别为548 ppm/℃和376 ppm/℃。实验结果表明,SOI硅磁敏三极管差分结构集成化芯片可以提高磁灵敏度、改善温度特性。
[Abstract]:Based on the analysis of the basic structure, working principle and characteristics of the planar structure silicon magnetosensitive transistor, the differential structure of the integrated SOI silicon-sensitive triode is given. The integrated structure is composed of two SOI silicon-sensitive transistors (PSMST1, PSMST2) and a collector load resistor (RL1, RL2) comprising an emitter (E), two base (B1, B2), two collectors (C1, C2) and two collector load resistors. according to the basic structure, an ATLAS software is adopted to construct a planar silicon magnetosensitive triode simulation model, the influence of the base length (L), the base width (w), the emission region width (WE) and the substrate type on the IC-VCE characteristic, the magnetic property and the temperature characteristic is studied, and the structural parameter optimization is realized, On this basis, the simulation model of the differential structure of SOI silicon-sensitive triode is constructed. Based on the above, in the device layer, the device layer is 100 crystal-to-P type high-resistance (F1000). 路 cm) On-chip research, design and fabrication of integrated SOI silicon-sensitive triode differential structure. By using a semiconductor parameter tester (Keithley 4200), a magnetic field generator system (CH-100), a multimeter (Agilent 34401A), a constant current source (Rigl SD120), a constant voltage source (Rigl DP832), and a high and low temperature test chamber (Obis GDJS-100LG-G), The IC-VCE characteristic, the magnetic property and the temperature characteristic test are carried out on the integrated SOI silicon-sensitive triode differential structure chip with different geometric structure sizes. According to the experimental results, the optimal geometric structure dimensions, WE, w and L are 400. m u.m,50. m and 100. m u.m, respectively, and when VDD = 3.5 V, IB = 0.5 mA, The absolute magnetic sensitivity of the collector voltage of the integrated chip is 68.97 mV/ T and 132.72 mV/ T, respectively, and the relative temperature coefficient of the collector voltage is 548 ppm/ 鈩，
本文编号：2508602
[Abstract]:Based on the analysis of the basic structure, working principle and characteristics of the planar structure silicon magnetosensitive transistor, the differential structure of the integrated SOI silicon-sensitive triode is given. The integrated structure is composed of two SOI silicon-sensitive transistors (PSMST1, PSMST2) and a collector load resistor (RL1, RL2) comprising an emitter (E), two base (B1, B2), two collectors (C1, C2) and two collector load resistors. according to the basic structure, an ATLAS software is adopted to construct a planar silicon magnetosensitive triode simulation model, the influence of the base length (L), the base width (w), the emission region width (WE) and the substrate type on the IC-VCE characteristic, the magnetic property and the temperature characteristic is studied, and the structural parameter optimization is realized, On this basis, the simulation model of the differential structure of SOI silicon-sensitive triode is constructed. Based on the above, in the device layer, the device layer is 100 crystal-to-P type high-resistance (F1000). 路 cm) On-chip research, design and fabrication of integrated SOI silicon-sensitive triode differential structure. By using a semiconductor parameter tester (Keithley 4200), a magnetic field generator system (CH-100), a multimeter (Agilent 34401A), a constant current source (Rigl SD120), a constant voltage source (Rigl DP832), and a high and low temperature test chamber (Obis GDJS-100LG-G), The IC-VCE characteristic, the magnetic property and the temperature characteristic test are carried out on the integrated SOI silicon-sensitive triode differential structure chip with different geometric structure sizes. According to the experimental results, the optimal geometric structure dimensions, WE, w and L are 400. m u.m,50. m and 100. m u.m, respectively, and when VDD = 3.5 V, IB = 0.5 mA, The absolute magnetic sensitivity of the collector voltage of the integrated chip is 68.97 mV/ T and 132.72 mV/ T, respectively, and the relative temperature coefficient of the collector voltage is 548 ppm/ 鈩，
本文编号：2508602
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