基于55nm工艺的12位高速低功耗流水线型ADC设计
发布时间：2019-07-05 15:24
【摘要】：随着通信及消费类电子的迅速发展,SOC(system-on-a-chip)片上系统得到了广泛应用。如今便携式电子设备逐渐深入人们的生活,SOC中集成的功能也越来越复杂和强大,因此低功耗高性能集成电路设计已经逐渐成为研究的重点和热点。近年来,半导体工艺特征尺寸大幅减小,这大幅提升了MOS晶体管的本征频率、降低了电路的功耗并有效提高了电路的集成度。然而工艺尺寸的减小也导致了器件的本征增益下降、供电电压降低等各种问题,从而加大了模拟集成电路的设计难度。这些问题在模数转换器的设计中尤为突出。因此,在现代SOC应用和工艺条件下设计一款满足低功耗高性能要求的ADC已成为一项巨大的挑战。本设计针对视频模拟前端的系统需求,基于HLMC 55nm CMOS混合信号工艺设计了一款低功耗12bit采样速率为160M/s的流水线型ADC。论文首先分析了衡量流水线型ADC的关键性能参数和影响系统性能的非理想性的来源,在此基础之上重点考察了目前业内常用的低功耗技术。在比较了各种技术之后选用了运放共享、嵌套gain boost运放、电容逐级递减等技术。然后根据这些技术对流水线型模数转换器进行了系统级分析、设计和规划,随后完成了晶体管级电路设计。最后基于深亚微米工艺版图设计思想完成了本课题的版图工作,后仿真结果表明在采样频率为160M/s,输入信号为39.1MHz的正弦信号情况下,该ADC的SFDR为83.05dB,SNDR为72.1dB,ENOB达到11.68bit,而功耗只有54mW,整体性能指标完全满足系统的预期设计要求。论文研究成果均基于深亚微米工艺完成,其对深亚微米下模拟集成电路设计,尤其是对混合信号电路设计及其相关版图绘制均具有良好的参考价值。此外,论文对pipelined ADC的低功耗设计也进行了深入分析,对SOC系统中低功耗应用的设计具有一定的参考意义和价值。
[Abstract]:With the rapid development of communication and consumer electronics, SOC (system-on-a-chip) on-chip system has been widely used. Nowadays, portable electronic devices are gradually deepening into people's lives, and the integration function in SOC is becoming more and more complex and powerful, so the design of low power consumption and high performance integrated circuits has gradually become the focus and focus of research. In recent years, the characteristic size of semiconductor process has been greatly reduced, which greatly improves the intrinsic frequency of MOS transistors, reduces the power consumption of the circuit and effectively improves the integration of the circuit. However, the reduction of process size also leads to the decrease of intrinsic gain and power supply voltage of the device, which makes the design of analog integrated circuit more difficult. These problems are particularly prominent in the design of analog-to-digital converter. Therefore, it has become a great challenge to design a ADC to meet the requirements of low power consumption and high performance under modern SOC applications and process conditions. In order to meet the system requirements of video analog front end, a streamline ADC. with low power consumption 12bit sampling rate of 160M/s is designed based on HLMC 55nm CMOS mixed signal process. Firstly, this paper analyzes the key performance parameters of streamline ADC and the sources of non-ideality that affect the performance of the system, and on this basis, focuses on the low power consumption technologies commonly used in the industry at present. After comparing all kinds of technologies, operational amplifier sharing, embedded gain boost operational amplifier, capacitance decreasing and so on are selected. Then, according to these technologies, the streamline analog-to-digital converter is analyzed, designed and planned at the system level, and then the transistor-level circuit design is completed. Finally, based on the deep submicron process layout design idea, the post-simulation results show that when the sampling frequency is 160m 鈮，
本文编号：2510621
[Abstract]:With the rapid development of communication and consumer electronics, SOC (system-on-a-chip) on-chip system has been widely used. Nowadays, portable electronic devices are gradually deepening into people's lives, and the integration function in SOC is becoming more and more complex and powerful, so the design of low power consumption and high performance integrated circuits has gradually become the focus and focus of research. In recent years, the characteristic size of semiconductor process has been greatly reduced, which greatly improves the intrinsic frequency of MOS transistors, reduces the power consumption of the circuit and effectively improves the integration of the circuit. However, the reduction of process size also leads to the decrease of intrinsic gain and power supply voltage of the device, which makes the design of analog integrated circuit more difficult. These problems are particularly prominent in the design of analog-to-digital converter. Therefore, it has become a great challenge to design a ADC to meet the requirements of low power consumption and high performance under modern SOC applications and process conditions. In order to meet the system requirements of video analog front end, a streamline ADC. with low power consumption 12bit sampling rate of 160M/s is designed based on HLMC 55nm CMOS mixed signal process. Firstly, this paper analyzes the key performance parameters of streamline ADC and the sources of non-ideality that affect the performance of the system, and on this basis, focuses on the low power consumption technologies commonly used in the industry at present. After comparing all kinds of technologies, operational amplifier sharing, embedded gain boost operational amplifier, capacitance decreasing and so on are selected. Then, according to these technologies, the streamline analog-to-digital converter is analyzed, designed and planned at the system level, and then the transistor-level circuit design is completed. Finally, based on the deep submicron process layout design idea, the post-simulation results show that when the sampling frequency is 160m 鈮，
本文编号：2510621
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