基于跨层设计的MPSoC核间高可靠通信体制研究
发布时间：2019-07-09 11:59
【摘要】：随着芯片集成度的提高和芯片特征尺寸的缩小,在单个芯片中集成的核心数目已经越来越多。片上网络由于其扩展性好、通信带宽高等特点,已经成为目前片上多核系统核间主流互连方案。但随着芯片特征尺寸的持续缩减,片上网络的故障率受串扰、耦合、单粒子翻转等因素的影响而持续增加,因此片上网络的容错设计成为近年来一个重要的研究热点。由于容错设计将不可避免的引入各种开销,如何平衡可靠性和开销就成为了核间通信体制的研究重点。本文对片上网络链路上的瞬时故障进行研究,提出了一套基于跨层设计的高可靠性核间通信体制。该体制不但可以有效提升核间通信的可靠性,而且不会引入过多的面积和功耗开销。首先,本文对片上网络的故障种类、故障成因及故障建模展开研究,指出现有片上网络链路容错方法存在诸如开销大等方面的问题。针对这些问题,本文采用了更合理、更直观的比特故障模型来表征片上网络的链路故障,并以该模型为基础开展容错传输方案的研究和设计。其次,本文针对数据包的可达性问题,提出了一种基于跨层设计的包头高可靠检纠错方法,用于保护包头中的关键路由信息。该容错设计主要由路由器中的轻量级检错模块、网络接口中的纠错模块以及相关的控制逻辑三部分组成。其中,包头在数据链路层进行检错,然后在传输层采用译码单元进行纠错,从而为包头提供高可靠性,以保证数据包能够到达正确的目的地。随后,在数据包可达的基础上,本文分析了片上网络低开销高可靠的优化空间,对有效载荷进行低开销高可靠的容错设计。该设计采用(72,64)汉明码在传输层对有效载荷检错和纠错,实现纠正1比特随机错误并检测2比特差错的功能,以确保有效载荷的可靠性。在本文的最后使用ESYNET软件仿真平台以及Synopsys公司的EDA工具对上述容错设计进行仿真验证,对数据包到达率、数据包平均时延、功耗和面积开销等指标进行分析评估,并与其它常用传输机制进行对比。由实验结果可知,本文提出的传输方案在保证核间通信高可靠性的同时,减少了片上网络硬件资源开销和传输时间开销,实现片上性能和开销的良好平衡。
文内图片：
图片说明：基于NoC的3×3同构MPSoC结构图
[Abstract]:With the improvement of chip integration and the reduction of chip feature size, the number of cores integrated in a single chip has become more and more. Because of its good expansibility and high communication bandwidth, on-chip network has become the mainstream interconnection scheme between cores of on-chip multi-core system. However, with the continuous reduction of chip feature size, the failure rate of on-chip network is affected by crosstalk, coupling, single-particle flip and other factors, so the fault-tolerant design of on-chip network has become an important research focus in recent years. Because fault-tolerant design will inevitably introduce all kinds of overhead, how to balance reliability and overhead has become the research focus of inter-core communication system. In this paper, the instantaneous fault on-chip network link is studied, and a set of high reliability inter-core communication system based on cross-layer design is proposed. This scheme can not only effectively improve the reliability of inter-core communication, but also does not introduce too much area and power consumption overhead. Firstly, this paper studies the fault types, fault causes and fault modeling of on-chip network, and points out that the existing fault-tolerant methods of on-chip network link have some problems, such as high overhead and so on. In order to solve these problems, a more reasonable and intuitive bit fault model is used to characterize the link failure of on-chip network, and the fault-tolerant transmission scheme is studied and designed on the basis of this model. Secondly, in order to solve the problem of packet reachability, a highly reliable detection and error correction method based on cross-layer design is proposed to protect the key routing information in the packet header. The fault-tolerant design is mainly composed of lightweight error detection module in router, error correction module in network interface and related control logic. Among them, the packet head detects errors in the data link layer, and then uses the decoding unit to correct the error in the transmission layer, thus providing high reliability for the packet header to ensure that the packet can reach the correct destination. Then, on the basis of packet accessibility, this paper analyzes the low overhead and high reliability optimization space of on-chip network, and carries out the fault-tolerant design of low overhead and high reliability for payloads. In this design, (72, 64) hamming codes are used to correct and correct payloads in the transport layer, so as to correct 1 bit random errors and detect 2 bits errors, so as to ensure the reliability of payloads. At the end of this paper, the ESYNET software simulation platform and Synopsys EDA tool are used to simulate and verify the fault-tolerant design, and the packet arrival rate, average packet delay, power consumption and area overhead are analyzed and evaluated, and compared with other common transmission mechanisms. The experimental results show that the transmission scheme proposed in this paper not only ensures the high reliability of inter-core communication, but also reduces the hardware resource overhead and transmission time overhead of on-chip network, and realizes a good balance between on-chip performance and overhead.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN47
本文编号：2512132
文内图片：
图片说明：基于NoC的3×3同构MPSoC结构图
[Abstract]:With the improvement of chip integration and the reduction of chip feature size, the number of cores integrated in a single chip has become more and more. Because of its good expansibility and high communication bandwidth, on-chip network has become the mainstream interconnection scheme between cores of on-chip multi-core system. However, with the continuous reduction of chip feature size, the failure rate of on-chip network is affected by crosstalk, coupling, single-particle flip and other factors, so the fault-tolerant design of on-chip network has become an important research focus in recent years. Because fault-tolerant design will inevitably introduce all kinds of overhead, how to balance reliability and overhead has become the research focus of inter-core communication system. In this paper, the instantaneous fault on-chip network link is studied, and a set of high reliability inter-core communication system based on cross-layer design is proposed. This scheme can not only effectively improve the reliability of inter-core communication, but also does not introduce too much area and power consumption overhead. Firstly, this paper studies the fault types, fault causes and fault modeling of on-chip network, and points out that the existing fault-tolerant methods of on-chip network link have some problems, such as high overhead and so on. In order to solve these problems, a more reasonable and intuitive bit fault model is used to characterize the link failure of on-chip network, and the fault-tolerant transmission scheme is studied and designed on the basis of this model. Secondly, in order to solve the problem of packet reachability, a highly reliable detection and error correction method based on cross-layer design is proposed to protect the key routing information in the packet header. The fault-tolerant design is mainly composed of lightweight error detection module in router, error correction module in network interface and related control logic. Among them, the packet head detects errors in the data link layer, and then uses the decoding unit to correct the error in the transmission layer, thus providing high reliability for the packet header to ensure that the packet can reach the correct destination. Then, on the basis of packet accessibility, this paper analyzes the low overhead and high reliability optimization space of on-chip network, and carries out the fault-tolerant design of low overhead and high reliability for payloads. In this design, (72, 64) hamming codes are used to correct and correct payloads in the transport layer, so as to correct 1 bit random errors and detect 2 bits errors, so as to ensure the reliability of payloads. At the end of this paper, the ESYNET software simulation platform and Synopsys EDA tool are used to simulate and verify the fault-tolerant design, and the packet arrival rate, average packet delay, power consumption and area overhead are analyzed and evaluated, and compared with other common transmission mechanisms. The experimental results show that the transmission scheme proposed in this paper not only ensures the high reliability of inter-core communication, but also reduces the hardware resource overhead and transmission time overhead of on-chip network, and realizes a good balance between on-chip performance and overhead.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN47
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