MEMS地震检波器中抽取滤波器的设计与FPGA实现

发布时间：2018-03-10 00:09

本文选题：MEMS　切入点：地震检波器　出处：《苏州大学》2015年硕士论文　论文类型：学位论文

【摘要】：MEMS地震检波器已经成为新一代高精度数字地震数据采集系统的核心部件,其优异的微弱信号检测能力使其能够胜任高精度勘探任务,因此逐渐成为地震检波器的发展趋势。作为MEMS地震检波器的核心技术部件之一,抽取滤波芯片是对前端伺服电路ASIC调制所产生的高速低位数据流进行数字滤波处理转换成低速高位数据流。本文主要工作即是设计出满足要求的抽取滤波器并以FPGA实现,首先介绍了MEMS地震检波器的背景及国内外研究现状,通过分析其对抽取滤波器的要求,提出了抽取滤波器的设计指标即设计要求。然后确定了抽取滤波器的整体架构,由以下三部分级联组成：①前端CIC滤波器,多倍数降采样及抗高频量化噪声混叠；②补偿FIR滤波器,补偿前端CIC滤波器造成的通带衰减,并进一步降采样；③末端等波纹FIR滤波器,完成系统精细滤波。接着通过Matlab仿真得到了满足设计指标的各级滤波器的参数,最后优化了CIC滤波器硬件实现结构,用FPGA实现了抽取滤波器的设计并通过了Modelsim仿真及板级调试。研究工作结果表明：①本文设计的抽取滤波器能够满足系统动态范围、信噪比、阻带衰减、通带纹波等性能指标；②本文优化了CIC滤波器的硬件实现结构,有效降低了系统功耗。
[Abstract]:MEMS geophone has become the core component of a new generation of high-precision digital seismic data acquisition system. Its excellent weak signal detection ability makes it capable of high-precision exploration task. As one of the core technical components of MEMS geophone, The decimation filter chip is used to convert the high-speed low data stream generated by the ASIC modulation of the front-end servo circuit into the low-speed high data stream. The main work of this paper is to design the decimation filter which meets the requirements and realize it with FPGA. This paper first introduces the background of MEMS seismograph and the present research situation at home and abroad. By analyzing the requirements of decimation filter, the design requirements of decimation filter are put forward, and then the whole structure of decimation filter is determined. It consists of the following three parts: 1 front-end CIC filter, multi-multiple demultiplexing and anti-high-frequency quantization noise aliasing FIR filter, compensating passband attenuation caused by front-end CIC filter, and further de-sampling 3-terminal equal-corrugated FIR filter. Through Matlab simulation, the parameters of all levels of filter satisfying the design index are obtained. Finally, the hardware implementation structure of CIC filter is optimized. The decimation filter is designed by using FPGA, and it is simulated by Modelsim and debugged at board level. The research results show that the decimation filter designed in this paper can satisfy the system dynamic range, signal-to-noise ratio (SNR) and stopband attenuation. In this paper, the hardware structure of CIC filter is optimized, and the power consumption of the system is reduced effectively.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：P631.436

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