基于SMIC 0.18um CMOS工艺的GPS卫星授时专用芯片物理设计

发布时间：2018-05-16 18:50

本文选题：GPS卫星授时 + 逻辑综合　；参考：《北京交通大学》2017年硕士论文

【摘要】：由于使用具有高精度的原子钟和地面维护系统,卫星导航系统能够提供准确的时间信息,因此卫星授时被广泛应用于通信系统、电子系统、军事领域等需要高精度的时间信息的领域。本论文将对一种低功耗GPS卫星授时算法的硬件代码进行物理实现,设计一款GPS卫星授时芯片并对流片结果进行测试。论文的物理设计包括从Verilog代码到tapeout整个流程。首先对RTL代码进行可测试逻辑综合(DFT,Design For Test),然后对综合网表进行静态时序分析(Pre-STA)确保时序正确;进行形式验证,保证电路功能符合设计要求;根据可测试性综合生成的测试协议文件,使用ATPG(AutomaticTest Pattern Generation)工具对设计进行自动测试向量生成和测试覆盖率分析;根据时序约束文件结合综合网表进行自动布局布线(Placing and Routing);提取寄生参数后再进行静态时序分析(Post-STA),最后再次对网表进行形式验证,确保布局布线后设计的时序与功能仍然满足设计要求;对版图进行DRC和LVS,导出GDSII版图进行流片。本论文的芯片电路中除了基本的数字模块外,还有两个模拟模块集成在芯片中,分别是电压调节器(VREG)和1024x38bits的双端口随机存取存储器(DPRAM),VREG产生1.8V的核心电路电源,DPRAM用来支持GPS卫星信号高速捕获算法。另外,电路还采用了门控时钟技术,在授时完成后切断捕获跟踪模块的时钟来减小功耗。论文采用SMIC 0.18um CMOS工艺对GPS卫星授时芯片进行了从RTL硬件代码到版图的完整后端设计,裸芯面积2.16x2.16mm~2,流片测试成功。该款芯片具有低功耗、低成本、小体积的特点,可广泛应用于日常生活中,拥有很可观的民用市场。
[Abstract]:Because of the use of high-precision atomic clocks and ground maintenance systems, satellite navigation systems can provide accurate time information, so satellite timing systems are widely used in communication systems, electronic systems, The military field and so on need the high precision time information domain. In this paper, the hardware code of a low power GPS satellite timing algorithm is implemented, and a GPS satellite timing chip is designed and the results of the convection chip are tested. The physical design of the thesis includes the whole process from Verilog code to tapeout. First, the RTL code is tested by DFT logic synthesis and design For test, then the static timing analysis of the integrated network table is carried out to ensure the timing is correct, the formal verification is carried out to ensure that the circuit functions meet the design requirements. According to the test protocol file generated by testability synthesis, the automatic test vector generation and test coverage analysis are carried out by using ATPG(AutomaticTest Pattern Generation tool. According to the timing constraint file and the comprehensive network table, the layout and routing is carried out automatically, the parasitic parameters are extracted and the static time sequence analysis is carried out, finally, the formal verification of the network table is carried out again. Ensure that the timing and function of the layout and routing design still meet the design requirements, and the layout of the DRC and LVS, the GDSII layout for streaming. In addition to the basic digital module, there are two analog modules integrated in the chip. Voltage regulator VREG) and 1024x38bits dual port random access memory (DPRAM / VREG) generate 1.8 V core circuit power supply DPRAM to support high speed acquisition algorithm for GPS satellite signals. In addition, the gated clock technology is used to reduce power consumption by cutting off the clock of the capture and tracking module. In this paper, the complete back-end design of GPS satellite timing chip from RTL hardware code to layout is carried out by SMIC 0.18um CMOS process. The bare core area is 2.16x2.16mm / 2, and the chip is tested successfully. The chip has the characteristics of low power consumption, low cost and small volume. It can be widely used in daily life and has a considerable civilian market.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：P228.4;TN402

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