面向低功耗共享Cache路适应划分算法研究

发布时间：2018-04-11 15:33

本文选题：路自适应 + 低功耗　；参考：《计算机科学》2014年07期

【摘要】：如何提高多核处理器的性能和降低多核处理器中Cache的功耗已经成为下一代多核处理器的研究热点。为了降低片上多核处理器的功耗,基于路适应算法可以采用一种新的动态划分机制,该机制主要由路分配模块和动态功耗控制模块组成。路分配模块在程序运行过程中根据处理器核所运行线程的工作集的大小调整处理器核所分配的Cache路。动态功耗控制模块利用程序运行的局部性原理,将处理器核所运行线程的工作空间控制在少数Cache路中。关闭剩余的Cache路,从而达到降低Cache功耗的目的。该机制使用Simics全系统模拟平台模拟多核处理器,并用SpecOMP测试集测试了系统的性能和功耗。与传统的Cache(Conventional L2Cache,C-L2)相比,其IPC提高了9.27%,功耗降低了10.95%。
[Abstract]:How to improve the performance of multi-core processors and reduce the power consumption of Cache in multi-core processors has become the research hotspot of the next generation multi-core processors.In order to reduce the power consumption of multi-core processor on chip, a new dynamic partition mechanism can be adopted based on path adaptation algorithm, which is mainly composed of path allocation module and dynamic power control module.The path allocation module adjusts the Cache path allocated by the processor core according to the size of the working set of the thread run by the processor core during the running process of the program.The dynamic power control module controls the workspace of the threads run by the processor core in a few Cache paths using the principle of locality of the program.The remaining Cache circuit is closed to reduce the power consumption of Cache.The mechanism simulates the multi-core processor using Simics full-system simulation platform, and tests the performance and power consumption of the system with SpecOMP test set.Compared with the traditional Cache(Conventional L2CacheC-L2), its IPC increases 9.27% and its power consumption decreases 10.95%.
【作者单位】：北京工业大学计算机学院;
【基金】：国家自然科学基金(61202076) 北京市教委科技计划面上项目(KM201210005022)资助
【分类号】：TP332

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